Workshop on System-Level Design for Signal and Information Processing

University of Maryland, College Park, October 24, 2016

10:00 -


Welcome and Opening Remarks, Shuvra Bhattacharyya

10:15 -


Keynote: Non-Functional Modeling of Computer Systems: How Much Is

Enough? Marilyn Wolf

11:00 -


Invited Talk: Processor Customization: Transport Triggering Approach, Jarmo Takala

11:45 -



12:00 -


Lightweight Dataflow Case Studies in Digital Predistortion and Embedded

Deep Learning, Lin Li

12:30 -



13:00 -


Invited Talk: Energy and Power Management in Coarse-Grained

Reconfigurable Platforms through Dataflow-based Strategies, Francesca Palumbo

13:45 -


Compact Modeling and Management of Reconfiguration in Digital

Channelizer Implementation, Adrian Sapio

14:15 -


Modeling Signal Processing Systems using the Dataflow Interchange

Format, Jiahao Wu

14:45 -


Closing Discussions and Wrapup

Abstracts of Invited Talks

Non-Functional Modeling of Computer Systems: How Much Is Enough?

Professor Marilyn Wolf, Georgia Institute of Technology, USA

Traditional software engineering divides requirements into functional and nonfunctional this approach gives little attention to nonfunctional requirements. However, characteristics such as performance, power consumption, thermal behavior, and reliability are critical for all classes of computer systems ranging from embedded to supercomputer. This talk puts forward the proposition that statistical models of nonfunctional characteristics is the best method by which system designs can be optimized for these characteristics. The combina- tion of complex models for nonfunctional characteristics and the complexity of computing platforms combine to drive us to statistical models. We will review modeling techniques for four nonfunctional system parameters: worst-case execution time, power consumption, ther- mal behavior, and reliability. We will then discuss our work on Markov decision processes as models to drive system design methodologies.

Processor Customization: Transport Triggering Approach

Professor Jarmo Takala, Tampere University of Technology, Finland

Signal processing tasks are more often executed in mobile devices where power consumption has become a major design constraint. At the same time, time-to-market requirements call for flexibility in design and implementations, thus software implementation are preferred over optimized VLSI designs. Unfortunately, programmable processors consume higher power than fixed-function hardware designs. Application-specific instruction-set processors offer a way to trade-off flexibility against power.

This talk introduces transport triggered architecture (TTA), which belongs to a class of statically scheduled computers. TTA processor contains parallel function units and reminds VLIW machines, but the operation execution is based on transport triggering paradigm where an instruction specifies only the data transports to be performed by the interconnection network. The execution of an operation is a side effect of an operand transport to a specific operand register of a function unit. TTAs, therefore, remind the data-flow computation paradigm, but the availability of operands is determined statically. The talk describes design environment starting from high-level languages, e.g., C or OpenCL, for mapping applications onto TTA processors. In the talk, the processor customization is illustrated with some examples.

Energy and Power Management in Coarse-Grained Reconfigurable Platforms through Dataflow- based Strategies

Professor Francesca Palumbo, Universit`a degli Studi di Sassari, Italy

Power reduction in modern embedded systems is a challenging issue exacerbated by their design complexity and heterogeneity, normally colliding with the need of cutting down de- signer effort to achieve shorter time to market. Reconfigurable Video Coding (RVC) adopts dataflow-based techniques to challenge those issues. Dynamic and incremental configuration and reconfiguration are favoured by the native formalism modularity, though required the definition of dedicated methodologies and tools (e.g. Orcc, Xronos, etc.) constituting, at the moment, the MPEG-RVC framework.

The Multi-Dataflow Composer (MDC) tool, born within MPEG-RVC studies, is capable of dataflow-to-hardware generation, addressing the automatic composition and management of runtime reconfigurable coarse-grained heterogeneous platforms. Lately MDC approach and dedicated extension of the tools have been devoted to energy/power management support.

Document version: 10/20/2016.