FDI-SRP: Foundations for Design and Implementation of Software Radio Platforms

Maryland DSPCAD Research Group
Project Webpage

In this project, we are developing new computational models and architectures for software radio applications. Our project is a collaborative project involving research groups at the University of Maryland (UMD), George Fox University (GFU), and Georgia Institute of Technology (GaTech).


Software radio promises substantial benefits to real-world systems by making them more flexible, interoperable, and easily upgradeable. While software radio systems have received considerable attention, many of the design methods in use today are ad hoc. We are developing a principled approach that works from models of computation through automated hardware/software synthesis down to architecture-related cost models. Since software radio applications center around manipulating various forms of signals, our approach emphasizes new models and methods for efficient, reliable signal processing.



Kapil Anand (UMD), Dr. Gordon Brebner (Xilinx), Prof. Ed Deprettere (Leiden University), Dr. Johan Eker (Ericsson), Dr. Joern Janneck (Xilinx), Dr. Jacob Kornerup (National Instruments), Prof. Marco Mattavelli (EPFL, Lausanne), Dr. Yong Rao (National Instruments), Dr. Mickael Raulet (Institut d' Electronique et de Telecommunications de Rennes), Nimish Sane (UMD), Dr. Guna Seetharaman (US Air Force Research Laboratory), Carl von Platen (Ericsson Research), Dr. Ian Wong (National Instruments).



We have been developing a unified framework, called functional DIF, for formal modeling of signal processing systems based on dataflow graphs. Various specialized forms of dataflow have been emerging that are targeted towards different types of signals, constraints, and application characteristics. The semantic range of signal-processing-oriented dataflow models has been significantly enhanced through such efforts, but efficient simulation and implementation for this expanding class of models has been limited.

We have shown how signal processing functions designed in other dataflow models are directly supported by a unified framework that we are developing for dataflow-based design. This framework is based on a novel form of signal-processing-oriented dataflow model of computation called enable-invoke dataflow (EIDF). EIDF-based modeling and functional DIF allow system designers to quickly compose and simulate representations from different specialized dataflow models, and perform rapid prototyping of static, quasi-static, and dynamic scheduling techniques. We have demonstrated how this approach can be applied to efficiently analyze and tune important trade-offs among different models and implementations.


We have been exploring the application of parameterized synchronous dataflow (PSDF) for modeling, design, and implementation of wireless communication systems. PSDF is a model of computation that results from integrating the parameterized dataflow meta-model for dynamic parameter management and reconfiguration with synchronous dataflow semantics. Using PSDF modeling techniques, we have explored FPGA implementation of 3GPP-Long Term Evolution (LTE), an important next-generation cellular standard. We have been experimenting with these methods using the National Instrument's LabVIEW FPGA design tool, a recently-introduced commercial platform for reconfigurable hardware implementation. We have also been developing a simulation tool for modeling and functional simulation of DSP applications using the parameterized synchronous dataflow (PSDF) model of computation. The simulation tool that we have been developing builds on the functional dataflow interchange format (DIF) environment that we have developed in our previous work. Our simulation tool allows designers to model applications in PSDF and simulate their functionality, including use of the dynamic parameter reconfiguration capabilities offered by PSDF. Based on our simulation tool, we have also been developing a structured design methodology for applying PSDF to the design and implementation of digital signal processing systems, with emphasis on FPGA-based systems.


We have been exploring techniques for modeling and analyzing trade-offs between buffer memory requirements and processing speed (throughput) in field programmable gate array (FPGA) implementation of digital signal processing (DSP) systems. Previously-developed techniques for such analysis suffer from high computational complexity, which limits their potential for use on complex application, and their incorporation into commercial design tools. By studying the execution patterns of FPGA-based DSP system implementations, we have been exploring novel ways of controlling execution and analyzing performance to yield an efficient form of execution-pattern / performance analysis co-design.


A list of publications from the FDI-SRP project, and PDF versions of selected publications can be found on the FDI-SRP Project Publications Page.


This research is supported by the U. S. National Science Foundation under grants NSF-0720596 (UMD), NSF-0720526 (GFU), and NSF-0720536 (GaTech).


This webpage was last updated on July 6, 2011.