Selected Publications of the Maryland DSP-CAD Research Group
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A BibTeX file
containing bibliographic
information for all publications listed here is also available.
Globally, this publication list is ordered in reverse chronological
order. Within a given year, the ordering is alphabetical (by author
name).
We are grateful to the following sponsors, who have supported the research
in Maryland DSPCAD Research Group at large:
Agilent Technologies; Angeles Design Systems, Inc.; the Austrian Marshall Plan
Foundation; Blue Halo / Intelligent Automation; CoolCAD Electronics; the
Defense Advanced Research Projects Agency; the Department of Homeland Security;
the Fulbright Specialists Program of the Council for International Exchange of
Scholars; IGI Technologies; Intel; the Intelligence Advanced Research Projects
Activity; the Laboratory for Physical Sciences; the Laboratory for
Telecommunication Sciences; Management Communications and Control, Inc.;
the Maryland Governor's Office of Crime Control and Prevention; the
Maryland Industrial Partnerships (MIPS) Program; the National Institutes of
Health; National Instruments; the National Institute of Standards and
Technology; the National Radio Astronomy Observatory; Northrop Grumman Corp.;
the Salisbury, Maryland Police Department;
the Semiconductor Research Corporation; Techno-Sciences, Inc.; Texas
Instruments, Inc.; Trident Systems, Inc.; the University of Maryland Graduate
School; the US Air Force Office of Scientific Research under the Dynamic Data
Driven Applications Systems (DDDAS) Program; the US Air Force Research
Laboratory; the US Army Research Laboratory; the US Army Research Office; and
the US National Science Foundation.
DSPCAD Group Website.
Bibliography generated from contentsIn.bib
- [liao2025x2]
- R. Liao, Z. Li, S. S.
Bhattacharyya, and G. York.
DensePoseGait: Dense
human pose part-guided for gait recognition.
IEEE Transactions on Biometrics, Behavior, and Identity Science,
7(1):33-46, January 2025.
- [xie2025x2]
- J. Xie, Y. Yan, A. Saxena, Q. Qiu,
J. Chen, H. Sun, R. Chen, and S. Bhattacharyya.
ShaderNN:
A lightweight and efficient inference engine for real-time applications on
mobile GPUs.
Neurocomputing, 611:1-14, 2025.
- [faye2024x2]
- J. Faye, N. Haggui, F. Kermarrec,
K. Martin, S. Bhattacharyya, J.-F. Nezan, and M. Pelcat.
Scratchy:
A class of adaptable architectures with software-managed communication for
edge streaming applications.
In Proceedings of the Workshop on Design and Architectures for Signal and
Image Processing, Munich, Germany, January 2024.
- [heag2024x2]
- J. Heagerty, S. Li, E. Lee,
S. Bhattacharyya, S. Bista, B. Brawn, B. Y. Feng, S. Jabbireddy, J. JaJa,
H. Kacorri, D. Li, D. Yarnell, M. Zwicker, and A. Varshney.
HoloCamera: Advanced
volumetric capture for cinematic-quality VR applications.
IEEE Transactions on Visualization and Computer Graphics,
30(5):2767-2775, 2024.
- [lee2024x3]
- H. Lee, Y. Zhang, H. Kwon, and
S. Bhattacharyya.
Exploring the potential
of synthetic data to replace real data.
In Proceedings of the International Conference on Image
Processing, Abu Dhabi, UAE, October 2024.
- [liao2024x3]
- R. Liao, Z. Li, S. Bhattacharyya,
and G. York.
ViewDiffGait: View
pyramid diffusion for gait recognition.
In Proceedings of the IEEE International Conference on Automatic Face and
Gesture Recognition, Istanbul, Turkey, May 2024.
- [carb2023x2]
- W. Carballo-Hernández,
M. Pelcat, S. Bhattacharyya, R. Galán, and F. Berry.
Flydeling: Streamlined
performance models for hardware acceleration of CNNs through system
identification.
ACM Transactions on Modeling and Performance Evaluation of Computing
Systems, 3(7):1-33, July 2023.
- [shen2023x4]
- Y.-T. Shen, H. Lee, H. Kwon, and
S. S. Bhattacharyya.
Progressive
transformation learning for leveraging virtual images in training.
In Proceedings of the IEEE Conference on Computer Vision and Pattern
Recognition, Vancouver, Canada, June 2023.
- [shen2023x5]
- Y.-T. Shen, Y. Lee, H. Kwon, D. M.
Conover, S. S. Bhattacharyya, N. Vale, J. D. Gray, G. J. Leong, K. Evensen,
and F. Skirlo.
Archangel:
A hybrid UAV-based human detection benchmark with position and pose
metadata.
IEEE Access, 11:80958-80972, 2023.
- [wu2023x2]
- X. Wu, D.-T. Lin, R. Chen, and S. S.
Bhattacharyya.
Jump-GRS:
a multi-phase approach to structured pruning of neural networks for neural
decoding.
Journal of Neural Engineering, 20(4):1-17, July 2023.
- [xie2023x3]
- J. Xie, R. Chen, and S. S.
Bhattacharyya.
A
parameter-optimization framework for neural decoding systems.
Frontiers in Neuroinformatics, 17:1-15, 2023.
- [xu2023x2]
- J. Xu, K. Sudusinghe, M. van der
Schaar, and S. S. Bhattacharyya.
Adaptive
data stream mining (DSM) systems.
In F. Darema, E. P. Blasch, S. Ravela, and A. J. Aved, editors, Handbook
of Dynamic Data Driven Application Systems --- Volume 2, pages
705-722. Springer, 2023.
- [bout2022x2]
- J. Boutellier, Y. Ma, J. Wu,
M. Khan, and S. S. Bhattacharyya.
VR-PRUNE: Decidable
variable-rate dataflow for signal processing systems.
IEEE Transactions on Signal Processing, 70:1819-1833, 2022.
- [wu2022x3]
- X. Wu, D.-T. Lin, R. Chen, and
S. Bhattacharyya.
Learning
compact DNN models for behavior prediction from calcium imaging of neural
activity.
Journal of Signal Processing Systems, 94:455-472, 2022.
- [lee2021x7]
- K. Lee, Y. Lee, A. Raina, Y. Liu,
J. Wu, C. Defrancisci, B. Riggan, and S. S. Bhattacharyya.
Software
synthesis from dataflow schedule graphs.
SN Applied Sciences, 3(2):1-20, January 2021.
Article No. 142.
- [wu2021x4]
- X. Wu, S. S. Bhattacharyya, and
R. Chen.
WGEVIA:
A graph level embedding method for microcircuit data.
Frontiers in Computational Neuroscience, 14:1-18, January
2021.
- [geng2020x2]
- J. Geng, H. Li, M. Kashef, Y. Liu,
R. Candell, and S. S. Bhattacharyya.
Integrating field
measurements into a model-based simulator for industrial communication
networks.
In Proceedings of the IEEE World Conference on Factory Communication
Systems, page 8 pages in online proceedings, Porto, Portugal, April
2020.
- [hang2020x3]
- R. Hang, Z. Li, Q. Liu,
P. Ghamisi, and S. Bhattacharyya.
Hyperspectral image
classification with attention aided CNNs.
IEEE Transactions on Geoscience and Remote Sensing, 2020.
IEEE Early Access Articles, DOI: 10.1109/TGRS.2020.3007921.
- [lee2020x5]
- K. Lee, X. Wu, Y. Lee, D.-T. Lin,
S. S. Bhattacharyya, and R. Chen.
Neural decoding on
imbalanced calcium imaging data with a network of support vector
machines.
Advanced Robotics, pages 1-12, 2020.
DOI: 10.1080/01691864.2020.1863259.
- [lee2020x7]
- Y. Lee, Y. Liu, K. Desnos,
L. Barford, and S. S. Bhattacharyya.
Passive-active flowgraphs for efficient
modeling and design of signal processing systems.
Journal of Signal Processing Systems, 92(10):1133-1151, October
2020.
- [lee2020x8]
- Y. Lee, J. Xie, E. Lee,
S. Sudarsanan, D.-T. Lin, R. Chen, and S. Bhattacharyya.
Real-time
neuron detection and neural signal extraction platform for miniature calcium
imaging.
Frontiers in Computational Neuroscience, 14:1-20, 2020.
- [lee2020x1]
- Y. Lee, J. Xie, E.-J. Lee, R. Chen,
and S. S. Bhattacharyya.
The neuron
detection and signal extraction platform: Introduction to NDSEP version
1.0.
Technical Report DSPCAD-TR-2020-01, Maryland DSPCAD Research Group, Department
of Electrical and Computer Engineering, University of Maryland at College
Park, April 2020.
- [sapi2020x5]
- A. Sapio, S. S. Bhattacharyya, and
M. Wolf.
Runtime adaptation in wireless
sensor nodes using structured learning.
ACM Transactions on Cyber-Physical Systems, 4(4):40:1-40:28, July
2020.
Article 40.
- [wu2020x2]
- J. Wu, J. Xie, A. Bardakoff,
T. Blattner, W. Keyrouz, and S. S. Bhattacharyya.
CGMBE:
A model-based tool for the design and implementation of real-time image
processing applications on CPU-GPU platforms.
Journal of Real-Time Image Processing, 2020.
- [bhat2019x2]
- S. S. Bhattacharyya,
E. Deprettere, R. Leupers, and J. Takala, editors.
Handbook
of Signal Processing Systems.
Springer, third edition, 2019.
ISBN: 978-3-319-91733-7 (Print); 978-3-319-91734-4 (Online).
- [lee2019x2]
- E.-J. Lee, W. Plishker, X. Liu,
T. Kane, S. S. Bhattacharyya, and R. Shekhar.
Segmentation of surgical
instruments in laparoscopic videos: training dataset generation and
deep-learning-based framework.
In Proceedings of SPIE (Medical Imaging), volume 10951, San Diego,
California, 2019.
DOI: 10.1117/12.2512994.
- [lee2019x3]
- K. Lee, Y. Lee, D.-T. Lin, S. S.
Bhattacharyya, and R. Chen.
Real-time calcium imaging based neural decoding with a support vector machine.
In Proceedings of the IEEE Biomedical Circuits and Systems
Conference, Nara, Japan, October 2019.
4 pages in online proceedings.
- [li2019x4]
- L. Li, C. Sau, T. Fanni, J. Li,
T. Viitanen, F. Christophe, F. Palumbo, L. Raffo, H. Huttunen, J. Takala, and
S. S. Bhattacharyya.
An integrated
hardware/software design methodology for signal processing systems.
Journal of Systems Architecture, 93:1-19, 2019.
- [liu2019x2]
- Y. Liu, L. Barford, and S. S.
Bhattacharyya.
Optimized implementation of
digital signal processing applications with gapless data acquisition.
EURASIP Journal on Advances in Signal Processing, 2019(19):1-13,
March 2019.
- [noor2019x4]
- D. F. Noor, Y. Li, Z. Li,
S. Bhattacharyya, and G. York.
Multi-scale gradient
image super-resolution for preserving key SIFT points in low-resolution
images.
Signal Processing: Image Communication, 78:236-245, October
2019.
- [thee2019x1]
- B. Theelen, E. F. Deprettere, and
S. S. Bhattacharyya.
Dynamic dataflow graphs.
In S. S. Bhattacharyya, E. F. Deprettere, R. Leupers, and J. Takala, editors,
Handbook of Signal Processing Systems, pages 1173-1210.
Springer, third edition, 2019.
- [bai2018x3]
- Y. Bai, S. S. Bhattacharyya, A. P.
Happonen, and H. Huttunen.
Elastic neural networks: A scalable
framework for embedded computer vision, 2018.
arXiv:1807.00453.
- [bhat2018x3]
- S. S. Bhattacharyya and J. Lilius.
Model-based
representations for dataflow schedules.
In Principles of Modeling, pages 88-105. Springer, 2018.
- [bout2018x1]
- J. Boutellier, J. Wu, H. Huttunen,
and S. S. Bhattacharyya.
PRUNE: Dynamic and decidable dataflow for signal processing on heterogeneous
platforms.
IEEE Transactions on Signal Processing, 2018.
To appear; preprint available on IEEE Xplore; DOI 10.1109/TSP.2017.2773424.
- [geng2018x4]
- J. Geng, H. Li, Y. Liu, Y. Liu,
M. Kashef, R. Candell, and S. S. Bhattacharyya.
Model-based cosimulation
for industrial wireless networks.
In Proceedings of the IEEE International Workshop on Factory
Communication Systems, pages 1-10, Imperia, Italy, June 2018.
- [lin2018x1]
- S. Lin, J. Wu, and S. S.
Bhattacharyya.
Memory-constrained vectorization and
scheduling of dataflow graphs for hybrid CPU-GPU platforms.
ACM Transactions on Embedded Computing Systems, 2018.
To appear; preprint available at url http://arxiv.org/abs/1711.11154.
- [liu2018x4]
- Y. Liu, L. Barford, and S. S.
Bhattacharyya.
Generalized graph connections for
dataflow modeling of DSP applications, 2018.
arXiv:1807.05721.
- [sapi2018x1]
- A. Sapio, L. Li, J. Wu, M. Wolf,
and S. S. Bhattacharyya.
Reconfigurable digital channelizer design using factored Markov decision
processes.
Journal of Signal Processing Systems, 2018.
To appear; preprint available at url http://arxiv.org/abs/1712.08340.
- [barf2017x1]
- L. Barford, S. S. Bhattacharyya,
and Y. Liu.
Data flow algorithms for processors with vector
extensions.
Journal of Signal Processing Systems, 87(1):21-31, April 2017.
- [blat2017x1]
- T. Blattner, W. Keyrouz, S. S.
Bhattacharyya, M. Halem, and M. Brady.
A hybrid task graph scheduler for high performance image processing workflows.
Journal of Signal Processing Systems, 89(3):457-467, December
2017.
- [fann2017x3]
- T. Fanni, L. Li, T. Viitanen,
C. Sau, R. Xie, F. Palumbo, L. Raffo, H. Huttunen, J. Takala, and S. S.
Bhattacharyya.
Hardware
design methodology using lightweight dataflow and its integration with low
power techniques.
Journal of Systems Architecture, 78:15-29, August 2017.
- [ha2017x1]
- S. Ha, J. Teich, C. Haubelt,
M. Glaß, T. Mitra, R. Dömer, P. Eles, A. Shrivastava,
A. Gerstlauer, and S. S. Bhattacharyya.
Introduction
to hardware/software codesign.
In S. Ha and J. Teich, editors, Handbook of Hardware/Software
Codesign, pages 1-24. Springer, 2017.
- [laws2017x1]
- W. Lawson, S. D. Secules,
S. Bhattacharyya, A. Elby, W. Hawkins, T. Dumitras, and N. Ramirez.
Traditional
versus hardware-driven introductory programming courses: a comparison of
student identity, efficacy and success.
In Proceedings of the ASEE Annual Conference & Exposition,
Columbus, Ohio, June 2017.
Paper ID #18951, 10 pages.
- [lee2017x3]
- K. Lee, B. S. Riggan, and S. S.
Bhattacharyya.
An accumulative
fusion architecture for discriminating people and vehicles using acoustic and
seismic signals.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, New Orleans, Louisiana, March 2017.
- [lee2017x5]
- Y. Lee, S. C. Madayambath, Y. Liu,
D. T. Lin, R. Chen, and S. S. Bhattacharyya.
Online learning in neural decoding using incremental linear discriminant
analysis.
In Proceedings of the IEEE International Conference on Cyborg and Bionic
Systems, pages 173-177, Beijing, China, October 2017.
- [li2017x2]
- L. Li, A. Ghazi, J. Boutellier,
L. Anttila, M. Valkama, and S. S. Bhattacharyya.
Evolutionary multiobjective
optimization for adaptive dataflow-based digital predistortion
architectures.
EAI Endorsed Transactions on Cognitive Communications, 3(10):1-9,
February 2017.
- [li2017x3]
- L. Li, A. Sapio, J. Wu, Y. Liu,
K. Lee, M. Wolf, and S. S. Bhattacharyya.
Design and implementation of adaptive signal processing systems using Markov
decision processes.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 170-175, Seattle,
Washington, July 2017.
(PDF)
- [lin2017x6]
- S. Lin, Y. Liu, K. Lee, L. Li,
W. Plishker, and S. S. Bhattacharyya.
The
DSPCAD framework for modeling and synthesis of signal processing
systems.
In S. Ha and J. Teich, editors, Handbook of Hardware/Software
Codesign, pages 1185-1219. Springer, 2017.
- [pelc2017x1]
- M. Pelcat, A. Mercat, K. Desnos,
L. Maggiani, Y. Liu, J. Heulot, J.-F. Nezan, W. Hamidouche, D. Menard, and
S. Bhattacharyya.
Models of architecture:
Application to ESL model-based energy consumption estimation.
Technical report, IETR/INSA Rennes; Scuola Superiore Sant'Anna, Pisa; Institut
Pascal; University of Maryland, College Park; Tampere University of
Technology, Tampere, February 2017.
- [zaki2017x1]
- G. F. Zaki, W. Plishker, S. S.
Bhattacharyya, and F. Fruth.
Implementation,
scheduling, and adaptation of partial expansion graphs on multicore
platforms.
Journal of Signal Processing Systems, 87(1):107-125, April
2017.
- [bens2016x1]
- H. Ben Salem, T. Damarla,
K. Sudusinghe, W. Stechele, and S. S. Bhattacharyya.
Adaptive tracking of
people and vehicles using mobile platforms.
EURASIP Journal on Advances in Signal Processing, 2016(65):1-12,
2016.
(PDF)
- [bhat2016x1]
- S. S. Bhattacharyya and M. Wolf.
Tools and methodologies for system-level
design.
In L. Lavagno, I. L. Markov, G. E. Martin, and L. K. Scheffer, editors,
Electronic Design Automation for Integrated Circuits Handbook ---
Volume 1: EDA for IC System Design, Verification, and Testing,
pages 39-58. CRC Press, Taylor & Francis Group, second edition, 2016.
- [gome2016x1]
- R. D. Gomez, B. Babadi,
S. Bhattacharyya, J. Goldhar, A. Khaligh, N. Mogul, W. S. Levine, M. Wu, and
R. Chellappa.
ENEE 101: On a gadgets
driven freshman laboratory course for improving first year retention
rates.
In Proceedings of the Annual First Year Engineering Experience
Conference, pages M1B-1-M1B-6, Columbus, Ohio, July 2016.
- [kim2016x1]
- S. C. Kim and S. S. Bhattacharyya.
A wideband front-end
receiver implementation on GPUs.
IEEE Transactions on Signal Processing, 64(10):2602-2612,
2016.
- [lee2016x1]
- K. Lee, H. Ben Salem, T. Damarla,
W. Stechele, and S. S. Bhattacharyya.
Prototyping
real-time tracking systems on mobile devices.
In Proceedings of the ACM International Conference on Computing
Frontiers, pages 301-308, Como, Italy, May 2016.
Invited paper.
(PDF)
- [li2016x4]
- L. Li, T. Fanni, T. Viitanen, R. Xie,
F. Palumbo, L. Raffo, H. Huttunen, J. Takala, and S. S. Bhattacharyya.
Low power design methodology for signal processing systems using lightweight
dataflow techniques.
In Proceedings of the Conference on Design and Architectures for Signal
and Image Processing, pages 81-88, Rennes, France, October 2016.
- [li2016x3]
- L. Li, A. Ghazi, J. Boutellier,
L. Anttila, M. Valkama, and S. S. Bhattacharyya.
Design space exploration and constrained multiobjective optimization for
digital predistortion systems.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 182-185, London,
England, July 2016.
- [li2016x7]
- L. Li, A. Ghazi, J. Boutellier,
L. Anttila, M. Valkama, and S. S. Bhattacharyya.
Evolutionary multiobjective optimization for adaptive dataflow-based digital
predistortion architectures.
EAI Endorsed Transactions on Cognitive Communications, 2016.
To appear.
- [li2016x1]
- L. Li, A. Ghazi, J. Boutellier,
L. Anttila, M. Valkama, and S. S. Bhattacharyya.
Evolutionary
multiobjective optimization for digital predistortion architectures.
In Proceedings of the International Conference on Cognitive Radio
Oriented Wireless Networks, pages 498-510, Grenoble, France, May
2016.
- [lin2016x1]
- S. Lin, Y. Liu, W. Plishker, and
S. S. Bhattacharyya.
A design framework for mapping
vectorized synchronous dataflow graphs onto CPU--GPU platforms.
In Proceedings of the International Workshop on Software and Compilers
for Embedded Systems, pages 20-29, Sankt Goar, Germany, May 2016.
- [sapi2016x1]
- A. Sapio, M. Wolf, and S. S.
Bhattacharyya.
Compact modeling and management of reconfiguration in digital channelizer
implementation.
In Proceedings of the IEEE Global Conference on Signal and Information
Processing, pages 595-599, Washington, D.C., December 2016.
- [wolf2016x1]
- M. Wolf, S. S. Bhattacharyya,
J. Florence, and A. E. Sapio.
Power and thermal modeling for communication systems.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 136-141, Dallas, Texas, October 2016.
- [zaki2016x1]
- G. F. Zaki, W. Plishker, S. S.
Bhattacharyya, and F. Fruth.
Implementation,
scheduling, and adaptation of partial expansion graphs on multicore
platforms.
Journal of Signal Processing Systems, 2016.
Online version available, print version to appear.
- [blat2015x1]
- T. Blattner, W. Keyrouz, M. Halem,
M. Brady, and S. S. Bhattacharyya.
A hybrid task graph
scheduler for high performance image processing workflows.
In Proceedings of the IEEE Global Conference on Signal and Information
Processing, pages 634-637, Orlando, Florida, December 2015.
- [chuk2015x1]
- I. Chukhman.
Profile- and Instrumentation-Driven Methods for Embedded Signal
Processing.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2015.
(PDF)
- [ghaz2015x1]
- A. Ghazi, J. Boutellier,
O. Silvén, S. Shahabuddin, M. Juntti, S. S. Bhattacharyya, and
L. Anttila.
Model-based design
and implementation of an adaptive digital predistortion filter.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 1-6, Hangzhou, China, October 2015.
- [jiao2015x1]
- Y. Jiao, K. Sudusinghe, and S. S.
Bhattacharyya.
Setting up the
DSPCAD lightweight dataflow environment: Setup guide for LIDE version
0.2.
Technical Report DSPCAD-TR-2015-01, Maryland DSPCAD Research Group, Department
of Electrical and Computer Engineering, University of Maryland at College
Park, April 2015.
- [kim2015x1]
- S. C. Kim and S. S. Bhattacharyya.
An efficient GPU
implementation of a multirate resampler for multicarrier systems.
In Proceedings of the IEEE Global Conference on Signal and Information
Processing, pages 751-755, Orlando, Florida, December 2015.
- [pelc2015x1]
- M. Pelcat, K. Desnos, L. Maggiani,
Y. Liu, J. Heulot, J.-F. Nezan, and S. S. Bhattacharyya.
Models of architecture.
Technical Report PREESM/2015-12TR01, IETR/INSA Rennes, 2015.
HAL Id: hal-01244470.
(PDF)
- [sudu2015x2]
- K. Sudusinghe.
Design Tools for Dynamic, Data-Driven, Stream Mining Systems.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2015.
(PDF)
- [sudu2015x1]
- K. Sudusinghe, Y. Jiao, H. Ben
Salem, M. van der Schaar, and S. S. Bhattacharyya.
Multiobjective
design optimization in the lightweight dataflow for DDDAS environment
(LiD4E).
In Proceedings of the International Conference on Computational
Science, pages 2563-2572, Reykjavik, Iceland, June 2015.
- [bhat2014x1]
- S. S. Bhattacharyya, W. Plishker,
N. Sane, K. Sudusinghe, and G. Zaki.
Setting up the
DSPCAD integrative command-line environment: Setup guide for DICE version
1.2.
Technical Report DSPCAD-TR-2014-01, Maryland DSPCAD Research Group, Department
of Electrical and Computer Engineering, University of Maryland at College
Park, May 2014.
- [bhat2014x2]
- S. S. Bhattacharyya, M. van der
Schaar, O. Atan, C. Tekin, and K. Sudusinghe.
Data-driven stream
mining systems for computer vision.
In B. Kisacanin and M. Gelautz, editors, Advances in Embedded Computer
Vision, Advances in Computer Vision and Pattern Recognition, pages
249-264. Springer, 2014.
- [chuk2014x1]
- I. Chukhman and S. S.
Bhattacharyya.
Instrumentation-driven
framework for validation of dataflow applications.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 1-6, Belfast, UK, October 2014.
- [kim2014x1]
- S. C. Kim and S. S. Bhattacharyya.
Implementation of a
high throughput low latency polyphase channelizer on GPUs.
EURASIP Journal on Advances in Signal Processing, 2014(141):1-10,
2014.
- [kim2014x2]
- S. C. Kim and S. S. Bhattacharyya.
Implementation of a
low complexity low latency arbitrary resampler on GPUs.
In Proceedings of the IEEE Dallas Circuits and Systems Conference,
pages 1-4, Dallas, Texas, October 2014.
- [lee2014x1]
- C.-S. Lee, W.-C. Chen, S. S.
Bhattacharyya, and T.-S. Lee.
Dynamic, data-driven spectrum
management in cognitive small cell networks.
In Proceedings of the International Conference on Signal Processing and
Communication Systems, pages 1-5, Gold Coast, Australia, December
2014.
- [lin2014x2]
- S. Lin, L.-H. Wang, A. Vosoughi,
J. R. Cavallaro, M. Juntti, J. Boutellier, O. Silvén, M. Valkama, and
S. S. Bhattacharyya.
Parameterized sets of dataflow modes and their application to implementation of
cognitive radio systems.
Journal of Signal Processing Systems, 2014.
To appear, pre-publication version available online from
url http://www.ece.umd.edu/DSPCAD/papers/lin2014x2.pdf.
(PDF)
- [sudu2014x1]
- K. Sudusinghe, I. Cho, M. van der
Schaar, and S. S. Bhattacharyya.
Model based design environment for data-driven embedded signal processing
systems.
In Proceedings of the International Conference on Computational
Science, pages 1193-1202, Cairns, Australia, June 2014.
(PDF)
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- Z. Zhou, W. Plishker, S. S.
Bhattacharyya, K. Desnos, M. Pelcat, and Jean-Francois Nezan.
Scheduling of
parallelized synchronous dataflow actors for multicore signal processing.
Journal of Signal Processing Systems, pages 1-20, 2014.
Online version published, print version to appear.
- [zhou2014x1]
- Z. Zhou, C. Shen, W. Plishker, and
S. S. Bhattacharyya.
Dataflow-based, cross-platform design
flow for DSP applications.
In A. Sangiovanni-Vincentelli, H. Zeng, M. Di Natale, and P. Marwedel,
editors, Embedded Systems Development: From Functional Models to
Implementations, volume 20 of Embedded Systems, pages
41-65. Springer, 2014.
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- S. S. Bhattacharyya,
E. Deprettere, R. Leupers, and J. Takala, editors.
Handbook of Signal
Processing Systems.
Springer, second edition, 2013.
ISBN: 978-1-4614-6858-5 (Print); 978-1-4614-6859-2 (Online).
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- I. Cho, T. Patyk, D. Guevorkian,
J. Takala, and S. Bhattacharyya.
Pipelined FFT for wireless
communications supporting 128-2014 / 1536 -point transforms.
In Proceedings of the IEEE Global Conference on Signal and Information
Processing, pages 1242-1245, Austin, Texas, December 2013.
- [cho2013x1]
- I. Cho, C. Shen, Y. Tachwali,
C. Hsu, and S. S. Bhattacharyya.
Configurable, resource-optimized FFT
architecture for OFDM communication.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages 2746-2750, Vancouver, Canada, May 2013.
- [cho2013x2]
- I. Cho, K. Sudusinghe, C. Shen,
J. McGee, and S. S. Bhattacharyya.
A system-level design approach for dynamic
resource coordination and energy optimization in sensor network
platforms.
In Proceedings of the IEEE Asilomar Conference on Signals, Systems, and
Computers, pages 1436-1441, Pacific Grove, California, November 2013.
Invited paper.
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- I. Chukhman, S. Lin, W. Plishker,
C. Shen, and S. S. Bhattacharyya.
Instrumentation-driven
model detection and actor partitioning for dataflow graphs.
International Journal of Embedded and Real-Time Communication
Systems, 4:1-21, June 2013.
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- K. Desnos, M. Pelcat, J.-F.
Nezan, S. S. Bhattacharyya, and S. Aridhi.
PiMM: Parameterized and interfaced
dataflow meta-model for MPSoCs runtime reconfiguration.
In Proceedings of the International Conference on Embedded Computer
Systems: Architectures, Modeling, and Simulation, pages 41-48, Samos,
Greece, July 2013.
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- S. C. Kim, W. L. Plishker, and S. S.
Bhattacharyya.
An efficient GPU implementation of an
arbitrary resampling polyphase channelizer.
In Proceedings of the Conference on Design and Architectures for Signal
and Image Processing, pages 231-238, Cagliari, Italy, October
2013.
- [lee2013x1]
- D. Lee, M. Wolf, and S. S.
Bhattacharyya.
High-performance and
low-energy buffer mapping method for multiprocessor DSP systems.
ACM Transactions on Embedded Computing Systems, 12(3):82:1-82:23,
2013.
Article No. 82.
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- X. Lu, M. Valkama, J. R. Cavallaro,
M. Juntti, J. Janhunen, and S. S. Bhattacharyya.
Subcarrier allocation and power control
with LTE-A carrier aggregation.
In Proceedings of the IEEE Global Conference on Signal and Information
Processing, pages 1214-1217, Austin, Texas, December 2013.
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- K. Sudusinghe, S. Won, M. van der
Schaar, and S. S. Bhattacharyya.
A novel framework for design and
implementation of adaptive stream mining systems.
In Proceedings of the IEEE International Conference on Multimedia and
Expo, pages 1-6, San Jose, California, July 2013.
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- L. Wang, C.-C. Shen, S. Wu, and
S. S. Bhattacharyya.
Parameterized scheduling
of topological patterns in signal processing dataflow graphs.
Journal of Signal Processing Systems, 71(3):275-286, June 2013.
DOI:10.1007/s11265-012-0719-x.
- [wang2013x2]
- L.-H. Wang, S. S. Bhattacharyya,
A. Vosoughi, J. Cavallaro, M. Juntti, J. Boutellier, O. Silven, and
M. Valkama.
Dataflow modeling and design for cognitive
radio networks.
In Proceedings of the International Conference on Cognitive Radio
Oriented Wireless Networks, pages 196-201, Washington, DC, July
2013.
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- S. Won, I. Cho, K. Sudusinghe,
J. Xu, Y. Zhang, M. van der Schaar, and S. S. Bhattacharyya.
A design methodology
for distributed adaptive stream mining systems.
In Proceedings of the International Conference on Computational
Science, pages 2482-2491, Barcelona, Spain, June 2013.
- [zaki2013x1]
- G. Zaki, W. Plishker, S. S.
Bhattacharyya, C. Clancy, and J. Kuykendall.
Integration of
dataflow-based heterogeneous multiprocessor scheduling techniques in GNU
radio.
Journal of Signal Processing Systems, 70(2):177-191, February
2013.
DOI:10.1007/s11265-012-0696-0.
- [zhou2013x2]
- Z. Zhou, K. Desnos, M. Pelcat,
J.-F. Nezan, W. Plishker, and S. S. Bhattacharyya.
Scheduling of parallelized synchronous
dataflow actors.
In Proceedings of the International Symposium on System-on-Chip,
pages 1-10, Tampere, Finland, October 2013.
- [chuk2012x1]
- I. Chukhman, W. Plishker, and
S. S. Bhattacharyya.
Instrumentation-driven
model detection for datafow graphs.
In Proceedings of the International Symposium on System-on-Chip,
pages 1-8, Tampere, Finland, October 2012.
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- H. Kee, C. Shen, S. S.
Bhattacharyya, I. Wong, Y. Rao, and J. Kornerup.
Mapping parameterized
cyclo-static dataflow graphs onto configurable hardware.
Journal of Signal Processing Systems, 66(3):285-301, March
2012.
- [kim2012x1]
- S. C. Kim, W. L. Plishker, S. S.
Bhattacharyya, and J. R. Cavallaro.
GPU-based acceleration of symbol timing
recovery.
In Proceedings of the Conference on Design and Architectures for Signal
and Image Processing, pages 1-8, Karlsruhe, Germany, October 2012.
- [shen2012x1]
- C. Shen, W. Plishker, and S. S.
Bhattacharyya.
Dataflow-based
design and implementation of image processing applications.
In L. Guan, Y. He, and S.-Y. Kung, editors, Multimedia Image and Video
Processing, pages 609-629. CRC Press, second edition, 2012.
Chapter 24.
- [shen2012x2]
- C. Shen, S. Wu, N. Sane, H. Wu,
W. Plishker, and S. S. Bhattacharyya.
Design and synthesis
for multimedia systems using the targeted dataflow interchange format.
IEEE Transactions on Multimedia, 14(3):630-640, June 2012.
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- J. Takala, S. S. Bhattacharyya,
and W. Sung.
Guest editors' introduction.
Journal of Signal Processing Systems, 69(3):225-226, December
2012.
Special issue on Design and Implementation of Signal Processing Systems.
- [wang2012x1]
- L. Wang, C. Shen, G. Seetharaman,
K. Palaniappan, and S. S. Bhattacharyya.
Multidimensional dataflow graph modeling and mapping for efficient GPU
implementation.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 300-305, Québec City, Canada, October 2012.
(PDF)
- [zaki2012x1]
- G. F. Zaki, W. Plishker, S. S.
Bhattacharyya, and F. Fruth.
Partial expansion graphs: Exposing parallelism and dynamic scheduling
opportunities for DSP applications.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 86-93, Delft, The
Netherlands, July 2012.
- [zhou2012x1]
- Z. Zhou, C. Shen, W. Plishker,
H. Wu, and S. S. Bhattacharyya.
Systematic integration of flowgraph- and module-level parallelism in
implementation of DSP applications on multiprocessor systems-on-chip.
In Proceedings of the International Conference on Signal
Processing, pages 402-408, Beijing, China, October 2012.
(PDF)
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- S. S. Bhattacharyya, J. Eker,
J. W. Janneck, C. Lucarz, M. Mattavelli, and M. Raulet.
Overview of the MPEG reconfigurable video coding framework.
Journal of Signal Processing Systems, 63(2):251-263, May 2011.
(PDF)
- [bhat2011x2]
- S. S. Bhattacharyya, W. Plishker,
N. Sane, C. Shen, and H. Wu.
Modeling and optimization of dynamic signal processing in resource-aware sensor
networks.
In Proceedings of the Workshop on Resources Aware Sensor and Surveillance
Networks in conjunction with IEEE International Conference on Advanced Video
and Signal-Based Surveillance, pages 449-454, Klagenfurt, Austria,
August 2011.
(PDF)
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- S. S. Bhattacharyya, W. Plishker,
C. Shen, and A. Gupta.
Teaching cross-platform design and testing methods for embedded systems using
DICE.
In Proceedings of the Workshop on Embedded Systems Education,
pages 38-45, Taipei, Taiwan, October 2011.
(PDF)
- [bhat2011x3]
- S. S. Bhattacharyya, W. Plishker,
C. Shen, N. Sane, and G. Zaki.
The DSPCAD integrative command line environment: Introduction to DICE
version 1.1.
Technical Report UMIACS-TR-2011-10, Institute for Advanced Computer Studies,
University of Maryland at College Park, 2011.
http://drum.lib.umd.edu/handle/1903/11422.
(PDF)
- [bhat2011x4]
- S. S. Bhattacharyya, C. Shen,
W. Plishker, N. Sane, and G. Zaki.
Using the DSPCAD integrative command-line environment: User's guide for
DICE version 1.1.
Technical Report UMIACS-TR-2011-13, Institute for Advanced Computer Studies,
University of Maryland at College Park, 2011.
http://hdl.handle.net/1903/11804.
(PDF)
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- R. Gu, J. W. Janneck, M. Raulet, and
S. S. Bhattacharyya.
Exploiting statically schedulable regions in dataflow programs.
Journal of Signal Processing Systems, 63(1):129-142, April 2011.
(PDF)
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- C. Hsu, J. Pino, and S. S.
Bhattacharyya.
Multithreaded simulation for synchronous dataflow graphs.
ACM Transactions on Design Automation of Electronic Systems,
16(3):25-1-25-23, June 2011.
(PDF)
- [kedi2011x1]
- S. Kedilaya, W. Plishker,
A. Purkovic, B. Johnson, and S. S. Bhattacharyya.
Model-based precision analysis and optimization for digital signal processors.
In Proceedings of the European Signal Processing Conference, pages
506-510, Barcelona, Spain, August 2011.
(PDF)
- [plis2011x2]
- W. Plishker, N. Sane, M. Kiemb,
and S. S. Bhattacharyya.
Heterogeneous design
in functional DIF.
In P. Stenström, editor, Transactions on High-Performance Embedded
Architectures and Compilers IV, volume 6760 of Lecture Notes in
Computer Science, pages 391-408. Springer Berlin / Heidelberg,
2011.
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- W. Plishker, G. Zaki, S. S.
Bhattacharyya, C. Clancy, and J. Kuykendall.
Applying graphics processor acceleration in a software defined radio
prototyping environment.
In Proceedings of the International Symposium on Rapid System
Prototyping, pages 67-73, Karlsruhe, Germany, May 2011.
(PDF)
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- N. Sane.
Rapid Prototyping of High Performance Signal Processing
Applications.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2011.
(PDF)
- [sane2011x1]
- N. Sane, H. Kee, G. Seetharaman,
and S. S. Bhattacharyya.
Topological patterns for scalable representation and analysis of dataflow
graphs.
Journal of Signal Processing Systems, 65(2):229-244, 2011.
(PDF)
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- C. Shen, W. Plishker, and S. S.
Bhattacharyya.
Dataflow-based design and implementation of image processing applications.
Technical Report UMIACS-TR-2011-11, Institute for Advanced Computer Studies,
University of Maryland at College Park, 2011.
http://drum.lib.umd.edu/handle/1903/11403.
(PDF)
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- C. Shen, L. Wang, I. Cho, S. Kim,
S. Won, W. Plishker, and S. S. Bhattacharyya.
The DSPCAD lightweight dataflow environment: Introduction to LIDE version
0.1.
Technical Report UMIACS-TR-2011-17, Institute for Advanced Computer Studies,
University of Maryland at College Park, 2011.
http://hdl.handle.net/1903/12147.
(PDF)
- [shen2011x1]
- C. Shen, H. Wu, N. Sane,
W. Plishker, and S. S. Bhattacharyya.
A design tool for efficient mapping of multimedia applications onto
heterogeneous platforms.
In Proceedings of the IEEE International Conference on Multimedia and
Expo, Barcelona, Spain, July 2011.
6 pages in online proceedings.
(PDF)
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- S. Wu.
Representation and scheduling of scalable dataflow graph topologies.
Master's thesis, Department of Electrical and Computer Engineering, University
of Maryland, College Park, 2011.
(PDF)
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- H. Wu, C. Shen, N. Sane, W. Plishker,
and S. S. Bhattacharyya.
A model-based schedule representation for heterogeneous mapping of dataflow
graphs.
In Proceedings of the International Heterogeneity in Computing
Workshop, pages 66-77, Anchorage, Alaska, May 2011.
(PDF)
- [zaki2011x1]
- G. Zaki, W. Plishker,
S. Bhattacharyya, C. Clancy, and J. Kuykendall.
Vectorization and mapping of software defined radio applications on
heterogeneous multi-processor platforms.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 31-36, Beirut, Lebanon, October 2011.
(PDF)
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- S. S. Bhattacharyya,
E. Deprettere, R. Leupers, and J. Takala, editors.
Handbook of Signal Processing Systems.
Springer, 2010.
(PDF)
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- S. S. Bhattacharyya, E. F.
Deprettere, and J. Keinert.
Dynamic and multidimensional dataflow graphs.
In S. S. Bhattacharyya, E. F. Deprettere, R. Leupers, and J. Takala, editors,
Handbook of Signal Processing Systems, pages 899-930. Springer,
2010.
(PDF)
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- J. Boutellier, S. S.
Bhattacharyya, and O. Silven.
A low-overhead scheduling methodology for fine-grained acceleration of signal
processing systems.
Journal of Signal Processing Systems, 60(3):333-343, September
2010.
(PDF)
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- Y-K Chen, C. Chakrabarti,
S. Bhattacharyya, and B. Bougard.
Signal processing on platforms with multiple cores: Part 2 --- design and
applications.
IEEE Signal Processing Magazine, 27(2):20-21, March 2010.
Guest Editors' Introduction.
(PDF)
- [gu2010x3]
- R. Gu.
Modeling and Optimization Techniques for Efficient Implementation of
Parallel Embedded Systems.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2010.
(PDF)
- [gu2010x2]
- R. Gu, S. S. Bhattacharyya, and W. S.
Levine.
Methods for efficient implementation of model predictive control on
multiprocessor systems.
In Proceedings of the IEEE International Conference on Control
Applications, pages 1357-1362, Yokohama, Japan, September 2010.
(PDF)
- [gu2010x4]
- R. Gu, J. Piat, M. Raulet, J. W.
Janneck, and S. S. Bhattacharyya.
Automated generation of an efficient MPEG-4 reconfigurable video coding
decoder implementation.
In Proceedings of the Conference on Design and Architectures for Signal
and Image Processing, Edinburgh, Scotland, October 2010.
(PDF)
- [kedi2010x1]
- S. Kedilaya.
Design and testing methodologies for signal processing systems using DICE.
Master's thesis, Department of Electrical and Computer Engineering, University
of Maryland, College Park, 2010.
(PDF)
- [kee2010x2]
- H. Kee.
Systematic Exploration of Trade-offs between Application Throughput and
Hardware Resource Requirements in DSP Systems.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2010.
(PDF)
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- H. Kee, S. S. Bhattacharyya, and
J. Kornerup.
Efficient static buffering to guarantee throughput-optimal FPGA
implementation of synchronous dataflow graphs.
In Proceedings of the International Conference on Embedded Computer
Systems: Architectures, Modeling, and Simulation, pages 136-143,
Samos, Greece, July 2010.
(PDF)
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- H. Kee, I. Wong, Y. Rao, and S. S.
Bhattacharyya.
FPGA-based design and implementation of the 3GPP-LTE physical layer using
parameterized synchronous dataflow techniques.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages 1510-1513, Dallas, Texas, March 2010.
(PDF)
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- D. Ko, N. Won, and S. S.
Bhattacharyya.
Buffer management for multi-application image processing on multi-core
platforms: Analysis and case study.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages 1662-1665, Dallas, Texas, March 2010.
(PDF)
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- J. Piat, S. S. Bhattacharyya, and
M. Raulet.
Loop transformations for interface-based hierarchies in SDF graphs.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 341-344, Rennes,
France, July 2010.
(PDF)
- [plis2010x2]
- W. Plishker, O. Dandekar, S. S.
Bhattacharyya, and R. Shekhar.
Utilizing hierarchical multiprocessing for medical image registration.
IEEE Signal Processing Magazine, 27(2):61-68, March 2010.
(PDF)
- [plis2010x3]
- W. Plishker, C. Shen, S. S.
Bhattacharyya, G. Zaki, S. Kedilaya, N. Sane, K. Sudusinghe, T. Gregerson,
J. Liu, and M. Schulte.
Model-based DSP implementation on FPGAs.
In Proceedings of the International Symposium on Rapid System
Prototyping, Fairfax, Virginia, June 2010.
Invited paper, DOI 10.1109/RSP_2010.SS4, 7 pages.
(PDF)
- [saha2010x1]
- S. Saha, N. K. Bambha, and S. S.
Bhattacharyya.
Design and implementation of embedded computer vision systems based on particle
filters.
Journal of Computer Vision and Image Understanding,
114(11):1203-1214, November 2010.
(PDF)
- [sane2010x2]
- N. Sane, C.-J. Hsu, J. L. Pino,
and S. S. Bhattacharyya.
Simulating dynamic communication systems using the core functional dataflow
model.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages 1538-1541, Dallas, Texas, March 2010.
(PDF)
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- N. Sane, H. Kee, G. Seetharaman,
and S. S. Bhattacharyya.
Scalable representation of dataflow graph structures using topological
patterns.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 13-18, San Francisco Bay Area, USA, October 2010.
(PDF)
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- C. Shen, W. Plishker, H. Wu, and
S. S. Bhattacharyya.
A lightweight dataflow approach for design and implementation of SDR systems.
In Proceedings of the Wireless Innovation Conference and Product
Exposition, pages 640-645, Washington DC, USA, November 2010.
(PDF)
- [shen2010x1]
- C. Shen, W. L. Plishker, D. Ko,
S. S. Bhattacharyya, and N. Goldsman.
Energy-driven distribution of signal processing applications across wireless
sensor networks.
ACM Transactions on Sensor Networks, 6(3), June 2010.
Article No. 24, 32 pages, DOI:10.1145/1754414.1754420.
(PDF)
- [wu2010x1]
- H. Wu, H. Kee, N. Sane, W. Plishker,
and S. S. Bhattacharyya.
Rapid prototyping for digital signal processing systems using parameterized
synchronous dataflow graphs.
In Proceedings of the International Symposium on Rapid System
Prototyping, pages 1-7, Fairfax, Virginia, June 2010.
DOI:10.1109/RSP_2010.10.
(PDF)
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- H. Wu, C. Shen, S. S. Bhattacharyya,
K. Compton, M. Schulte, M. Wolf, and T. Zhang.
Design and implementation of real-time signal processing applications on
heterogeneous multiprocessor arrays.
In Proceedings of the IEEE Asilomar Conference on Signals, Systems, and
Computers, pages 2121-2125, Pacific Grove, California, November 2010.
DOI:10.1109/ACSSC.2010.5757924. Invited paper.
(PDF)
- [bhat2009x1]
- S. S. Bhattacharyya, S. Kedilaya,
W. Plishker, N. Sane, C. Shen, and G. Zaki.
The DSPCAD integrative command line environment: Introduction to DICE
version 1.
Technical Report UMIACS-TR-2009-13, Institute for Advanced Computer Studies,
University of Maryland at College Park, August 2009.
(PDF)
- [bhat2009x2]
- S. S. Bhattacharyya, S. Kedilaya,
W. Plishker, N. Sane, C. Shen, and G. Zaki.
Using the DSPCAD integrative command-line environment: User's guide for
DICE version 1.0.
Technical Report DSPCAD-TR-2009-01, Maryland DSPCAD Research Group, Department
of Electrical and Computer Engineering, University of Maryland at College
Park, 2009.
(PDF)
- [chen2009x3]
- Y-K Chen, C. Chakrabarti,
S. Bhattacharyya, and B. Bougard.
Signal processing on platforms with multiple cores: Part 1 --- overview and
methodologies.
IEEE Signal Processing Magazine, 26(6):24-25, November 2009.
Guest Editors' Introduction.
(PDF)
- [chen2009x2]
- Y-K Chen, L-K Liu, and S. S.
Bhattacharyya.
Guest editorial: Special issue on multi-core enabled multimedia applications &
architectures.
Journal of Signal Processing Systems, 57(2):121-122, November
2009.
(PDF)
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- R. Gu, S. S. Bhattacharyya, and
W. Levine.
Dataflow-based implementation of model-predictive control.
In Proceedings of the American Control Conference, pages
2343-2349, St. Louis, Missouri, June 2009.
(PDF)
- [gu2009x4]
- R. Gu, S. S. Bhattacharyya, and W. S.
Levine.
Improving the performance of active set based model predictive controls by
dataflow methods.
In Proceedings of the IEEE Conference on Decision and Control,
pages 339-344, Shanghai, China, December 2009.
(PDF)
- [gu2009x1]
- R. Gu, J. Janneck, M. Raulet, and
S. S. Bhattacharyya.
Exploiting statically schedulable regions in dataflow programs.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages 565-568, Taipei, Taiwan, April 2009.
(PDF)
- [gu2009x3]
- R. Gu, J. W. Janneck, S. S.
Bhattacharyya, M. Raulet, M. Wipliez, and W. Plishker.
Exploring the concurrency of an MPEG RVC decoder based on dataflow program
analysis.
IEEE Transactions on Circuits and Systems for Video Technology,
19(11):1646-1657, November 2009.
(PDF)
- [kee2009x1]
- H. Kee, S. S. Bhattacharyya,
N. Petersen, and J. Kornerup.
Resource-efficient acceleration of 2-dimensional fast fourier transform
computations on FPGAs.
In Proceedings of the International Conference on Distributed Smart
Cameras, Como, Italy, August 2009.
8 pages in online proceedings.
(PDF)
- [lee2009x1]
- D. Lee, S. S. Bhattacharyya, and
W. Wolf.
High-performance buffer mapping to exploit DRAM concurrency in multiprocessor
DSP systems.
In Proceedings of the International Symposium on Rapid System
Prototyping, pages 137-144, Paris, France, June 2009.
DOI:10.1109/RSP.2009.34.
(PDF)
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- S. Liu, K. Salama, and
S. Bhattacharyya.
Special issue on selected papers from BiOCAS 2008: Guest editors'
introduction.
IEEE Transactions on Biomedical Circuits and Systems,
3(6):361-362, December 2009.
(PDF)
- [plis2009x1]
- W. Plishker, N. Sane, and S. S.
Bhattacharyya.
A generalized scheduling approach for dynamic dataflow applications.
In Proceedings of the Design, Automation and Test in Europe Conference
and Exhibition, pages 111-116, Nice, France, April 2009.
(PDF)
- [plis2009x2]
- W. Plishker, N. Sane, and S. S.
Bhattacharyya.
Mode grouping for more effective generalized scheduling of dynamic dataflow
applications.
In Proceedings of the Design Automation Conference, pages
923-926, San Francisco, California, July 2009.
(PDF)
- [saha2009x1]
- S. Saha, V. Kianzad, J.Schlessman,
G.Aggarwal, S. S. Bhattacharyya, W.Wolf, and R.Chellappa.
An architectural level design methodology for smart camera applications.
International Journal of Embedded Systems, 4(1):83-97, 2009.
(PDF)
- [shen2009x1]
- C. Shen and S. S. Bhattacharyya.
System-level clustering and timing analysis for GALS-based dataflow
architectures.
In Proceedings of the ACM International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems, Austin, Texas,
February 2009.
(PDF)
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- S. Sriram and S. S. Bhattacharyya.
Embedded Multiprocessors: Scheduling and Synchronization.
CRC Press, second edition, 2009.
ISBN:1420048015.
(PDF)
- [zaki2009x1]
- G. Zaki, W. Plishker, T. OShea,
N. McCarthy, C. Clancy, E. Blossom, and S. S. Bhattacharyya.
Integration of dataflow optimization techniques into a software radio design
framework.
In Proceedings of the IEEE Asilomar Conference on Signals, Systems, and
Computers, pages 243-247, Pacific Grove, California, November 2009.
Invited paper.
(PDF)
- [bhat2008x3]
- S. S. Bhattacharyya, J. Bier,
W. K. Gass, R. K. Krishnamurthy, E. A. Lee, and K. Konstantinides.
Advances in hardware design and implementation of signal processing systems.
IEEE Signal Processing Magazine, 25(6):175-180, November 2008.
(PDF)
- [bhat2008x2]
- S. S. Bhattacharyya, G. Brebner,
J. Eker, J. W. Janneck, M. Mattavelli, and M. Raulet.
How to make stream processing more mainstream.
In Proceedings of the Workshop on Streaming Systems, Lake Como,
Italy, November 2008.
3 pages.
(PDF)
- [bhat2008x4]
- S. S. Bhattacharyya, G. Brebner,
J. Eker, J. W. Janneck, M. Mattavelli, C. von Platen, and M. Raulet.
OpenDF --- a dataflow toolset for reconfigurable hardware and multicore
systems.
In Proceedings of the Swedish Workshop on Multi-Core Computing,
pages 43-49, Ronneby, Sweden, November 2008.
(PDF)
- [dand2008x2]
- O. Dandekar.
High-performance 3D Image Processing Architectures for Image-guided
Interventions.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2008.
(PDF)
- [dand2008x1]
- O. Dandekar, W. Plishker, S. S.
Bhattacharyya, and R. Shekhar.
Multiobjective optimization of FPGA-based medical image registration.
In Proceedings of the IEEE Symposium on FPGAs for Custom Computing
Machines, pages 183-192, Palo Alto, CA, April 2008.
(PDF)
- [falk2008x1]
- J. Falk, J. Keinert, C. Haubelt,
J. Teich, and S. S. Bhattacharyya.
A generalized static data flow clustering algorithm for MPSoC scheduling of
multimedia applications.
In Proceedings of the International Conference on Embedded
Software, pages 189-198, Atlanta, Georgia, October 2008.
(PDF)
- [guzm2008x2]
- V. Guzma, S. S. Bhattacharyya,
P. Kellomaki, and J. Takala.
An integrated ASIP design flow for digital signal processing applications.
In Proceedings of the IEEE International Symposium on Applied Sciences in
Biomedical and Communication Technologies, pages 1-5, Aalborg,
Denmark, October 2008.
Invited paper.
(PDF)
- [guzm2008x1]
- V. Guzma, S. S. Bhattacharyya,
P. Kellomaki, and J. Takala.
Trade-offs in mapping high-level dataflow graphs onto ASIPs.
In Proceedings of the International Symposium on System-on-Chip,
pages 1-4, Tampere, Finland, November 2008.
(PDF)
- [hsu2008x1]
- C. Hsu, J. L. Pino, and S. S.
Bhattacharyya.
Multithreaded simulation for synchronous dataflow graphs.
In Proceedings of the Design Automation Conference, pages
331-336, Anaheim, California, June 2008.
(PDF)
- [kee2008x1]
- H. Kee, N. Petersen, J. Kornerup,
and S. S. Bhattacharyya.
Systematic generation of FPGA-based FFT implementations.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages 1413-1416, Las Vegas, Nevada, March 2008.
(PDF)
- [kisa2008x1]
- B. Kisacanin, S. S. Bhattacharyya,
and S. Chai, editors.
Embedded
Computer Vision.
Springer, 2008.
(PDF)
- [ko2008x1]
- M. Ko, C. Shen, and S. S.
Bhattacharyya.
Memory-constrained block processing for DSP software optimization.
Journal of Signal Processing Systems, 50(2):163-177, February
2008.
(PDF)
- [plis2008x3]
- W. Plishker, O. Dandekar, S. S.
Bhattacharyya, and R. Shekhar.
Towards systematic exploration of tradeoffs for medical image registration on
heterogeneous platforms.
In Proceedings of the IEEE Biomedical Circuits and Systems
Conference, pages 53-56, Baltimore, Maryland, November 2008.
(PDF)
- [plis2008x1]
- W. Plishker, N. Sane, M. Kiemb,
K. Anand, and S. S. Bhattacharyya.
Functional DIF for rapid prototyping.
In Proceedings of the International Symposium on Rapid System
Prototyping, pages 17-23, Monterey, California, June 2008.
(PDF)
- [plis2008x2]
- W. Plishker, N. Sane, M. Kiemb,
and S. S. Bhattacharyya.
Heterogeneous design in functional DIF.
In Proceedings of the International Workshop on Systems, Architectures,
Modeling, and Simulation, pages 157-166, Samos, Greece, July 2008.
(PDF)
- [saha2008x5]
- S. Saha and S. S. Bhattacharyya.
Design methodology for embedded computer vision systems.
In B. Kisacanin, S. S. Bhattacharyya, and S. Chai, editors, Embedded
Computer Vision, pages 27-47. Springer, 2008.
(PDF)
- [saha2008x2]
- S. Saha, N. Bambha, and S. S.
Bhattacharyya.
A parameterized design framework for hardware implementation of particle
filters.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages 1449-1452, Las Vegas, Nevada, March 2008.
(PDF)
- [saha2008x4]
- S. Saha, S. Puthenpurayil,
J. Schlessman, S. S. Bhattacharyya, and W. Wolf.
The signal passing interface and its application to embedded implementation of
smart camera applications.
Proceedings of the IEEE, 96(10):1576-1587, October 2008.
Invited paper.
(PDF)
- [saha2008x1]
- S. Saha, J. Schlessman, S. S.
Bhattacharyya, and W. Wolf.
An optimized message passing framework for parallel implementation of signal
processing applications.
In Proceedings of the Design, Automation and Test in Europe Conference
and Exhibition, pages 1220-1225, Munich, Germany, March 2008.
(PDF)
- [sen2008x1]
- M. Sen, Y. Hemaraj, W. Plishker,
R. Shekhar, and S. S. Bhattacharyya.
Model-based mapping of reconfigurable image registration on FPGA platforms.
Journal of Real-Time Image Processing, 2008.
14 pages, doi:10.1007/s11554-008-0075-z.
(PDF)
- [shen2008x3]
- C. Shen.
Energy-driven Optimization of Hardware and Software for Distributed
Embedded Systems.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2008.
(PDF)
- [shen2008x1]
- C. Shen, R. Kupershtok, S. Adl,
S. S. Bhattacharyya, N. Goldsman, and M. Peckerar.
Sensor support systems for asymmetric threat countermeasures.
IEEE Sensors Journal, 8(6):682-692, June 2008.
(PDF)
- [shen2008x2]
- C. Shen, W. Plishker, and S. S.
Bhattacharyya.
Design and optimization of a distributed, embedded speech recognition system.
In Proceedings of the International Workshop on Parallel and Distributed
Real-Time Systems, pages 1-8, Miami, Florida, April 2008.
8 pages.
(PDF)
- [yao2008x1]
- A. Yao, J. Gu, G. Qu, and S. S.
Bhattacharyya.
Energy efficient implementation of G.729 for wireless VoIP applications.
In Proceedings of the International Conference on Advanced Infocomm
Technology, Da Meisha, China, July 2008.
7 pages.
(PDF)
- [bout2007x1]
- J. Boutellier, S. S.
Bhattacharyya, and O. Silven.
Low-overhead run-time scheduling for fine-grained acceleration of signal
processing systems.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 457-462, Shanghai, China, October 2007.
(PDF)
- [hsu2007x3]
- C. Hsu.
Dataflow Integration and Simulation Techniques for DSP System Design
tools.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, April 2007.
(PDF)
- [hsu2007x2]
- C. Hsu and S. S. Bhattacharyya.
Cycle-breaking techniques for scheduling synchronous dataflow graphs.
Technical Report UMIACS-TR-2007-12, Institute for Advanced Computer Studies,
University of Maryland at College Park, February 2007.
Also Computer Science Technical Report CS-TR-4859.
(PDF)
- [hsu2007x4]
- C Hsu, I. Corretjer, M. Ko.,
W. Plishker, and S. S. Bhattacharyya.
Dataflow interchange format: Language reference for DIF language version 1.0,
user's guide for DIF package version 1.0.
Technical Report UMIACS-TR-2007-32, Institute for Advanced Computer Studies,
University of Maryland at College Park, June 2007.
Also Computer Science Technical Report CS-TR-4871.
(PDF)
- [hsu2007x1]
- C. Hsu, M. Ko, S. S. Bhattacharyya,
S. Ramasubbu, and J. L. Pino.
Efficient simulation of critical synchronous dataflow graphs.
ACM Transactions on Design Automation of Electronic Systems,
12(3):21, 2007.
28 pages.
(PDF)
- [hua2007x1]
- S. Hua, G. Qu, and S. S.
Bhattacharyya.
Probabilistic design of multimedia embedded systems.
ACM Transactions on Embedded Computing Systems, 6(3):15, 2007.
24 pages.
(PDF)
- [ko2007x2]
- M. Ko, P. K. Murthy, and S. S.
Bhattacharyya.
Beyond single appearance schedules: efficient DSP software synthesis using
recursive procedure calls.
ACM Transactions on Embedded Computing Systems, 6(2):14, May 2007.
23 pages.
(PDF)
- [ko2007x1]
- M. Ko, C. Zissulescu,
S. Puthenpurayil, S. S. Bhattacharyya, B. Kienhuis, and E. Deprettere.
Parameterized looped schedules for compact representation of execution
sequences in DSP hardware and software implementation.
IEEE Transactions on Signal Processing, 55(6):3126-3138, June
2007.
(PDF)
- [plis2007x2]
- W. Plishker, O. Dandekar, S. S.
Bhattacharyya, and R. Shekhar.
A taxonomy for medical image registration acceleration techniques.
In Proceedings of the IEEE-NIH Life Science Systems and Applications
Workshop, pages 215-218, Bethesda, Maryland, November 2007.
(PDF)
- [plis2007x1]
- W. Plishker, O. Dandekar, S. S.
Bhattacharyya, and R. Shekhar.
Towards a heterogeneous medical image registration acceleration platform.
In Proceedings of the IEEE Biomedical Circuits and Systems
Conference, pages 231-234, Montreal, Canada, November 2007.
(PDF)
- [puth2007x1]
- S. Puthenpurayil, R. Gu, and S. S.
Bhattacharyya.
Energy-aware data compression for wireless sensor networks.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, volume 2, pages 45-48, Honolulu, Hawaii, April
2007.
(PDF)
- [saha2007x3]
- S. Saha.
Design Methodology for Embedded Computer Vision Systems.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2007.
(PDF)
- [salm2007x1]
- P. Salmela, R. Gu, S. S.
Bhattacharyya, and J. Takala.
Efficient parallel memory organization for turbo decoders.
In Proceedings of the European Signal Processing Conference, pages
831-835, Poznan, Poland, September 2007.
(PDF)
- [sen2007x1]
- M. Sen, I. Corretjer, F. Haim,
S. Saha, J. Schlessman, T. Lv, S. S. Bhattacharyya, and W. Wolf.
Dataflow-based mapping of computer vision algorithms onto FPGAs.
EURASIP Journal on Embedded Systems, 2007:Article ID 49236, 12
pages, 2007.
doi:10.1155/2007/49236.
(PDF)
- [shen2007x5]
- C. Shen, R. Kupershtok, S. S.
Bhattacharyya, and N. Goldsman.
Design and implementation of a device network application for distributed
line-crossing recognition.
In Proceedings of the International Semiconductor Device Research
Symposium, College Park, Maryland, December 2007.
(PDF)
- [shen2007x3]
- C. Shen, R. Kupershtok, S. S.
Bhattacharyya, and N. Goldsman.
Design techniques for streamlined integration and fault tolerance in a
distributed sensor system for line-crossing recognition.
In Proceedings of the International Workshop on Distributed Sensor
Systems, pages 95-1-95-6, Honolulu, Hawaii, August 2007.
(PDF)
- [shen2007x1]
- C. Shen, R. Kupershtok, B. Yang,
F. M. Vanin, X. Shao, D. Sheth, N. Goldsman, Q. Balzano, and S. S.
Bhattacharyya.
Compact, low power wireless sensor network system for line crossing
recognition.
In Proceedings of the International Symposium on Circuits and
Systems, pages 2506-2509, New Orleans, Louisiana, May 2007.
(PDF)
- [shen2007x4]
- C. Shen, W. Plishker, S. S.
Bhattacharyya, and N. Goldsman.
An energy-driven design methodology for distributing DSP applications across
wireless sensor networks.
In Proceedings of the IEEE Real-Time Systems Symposium, pages
214-223, Tucson, Arizona, December 2007.
(PDF)
- [bhat2006x2]
- S. S. Bhattacharyya and W. S.
Levine.
Optimization of signal processing software for control system implementation.
In Proceedings of the IEEE Symposium on Computer-Aided Control Systems
Design, pages 1562-1567, Munich, Germany, October 2006.
Invited paper.
(PDF)
- [bhat2006x1]
- S. S. Bhattacharyya and W. Wolf.
Tools and methodologies for system-level design.
In L. Scheffer, L. Lavagno, and G. Martin, editors, Electronic Design
Automation for Integrated Circuits Handbook --- Volume 1: EDA for IC
System Design, Verification, and Testing, pages 3-1-3-19. Taylor &
Francis Group, 2006.
(PDF)
- [corr2006x1]
- I. Corretjer and S. S.
Bhattacharyya.
DIFdoc: a standard format for visualizing hierarchical dataflow
representations.
In Proceedings of the Annual Workshop on High Performance Embedded
Computing, pages 71-72, Lexington, Massachusetts, September 2006.
(PDF)
- [corr2006x2]
- I. Corretjer, C. Hsu, and S. S.
Bhattacharyya.
Configuration and representation of large-scale dataflow graphs using the
dataflow interchange format.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 10-15, Banff, Canada, October 2006.
(PDF)
- [depr2006x1]
- E. F. Deprettere, T. Stefanov,
S. S. Bhattacharyya, and M. Sen.
Affine nested loop programs and their binary cyclo-static dataflow
counterparts.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 186-190, Steamboat
Springs, Colorado, September 2006.
(PDF)
- [haim2006x1]
- F. Haim, M. Sen, D. Ko, S. S.
Bhattacharyya, and W. Wolf.
Mapping multimedia applications onto configurable hardware with parameterized
cyclo-static dataflow graphs.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages III-1052-III-1055, May 2006.
(PDF)
- [hema2006x1]
- Y. Hemaraj, M. Sen, R. Shekhar,
and S. S. Bhattacharyya.
Model-based mapping of image registration applications onto configurable
hardware.
In Proceedings of the IEEE Asilomar Conference on Signals, Systems, and
Computers, pages 1453-1457, Pacific Grove, California, October 2006.
Invited paper.
(PDF)
- [hsu2006x1]
- C. Hsu, S. Ramasubbu, M. Ko, J. L.
Pino, and S. S. Bhattacharyya.
Efficient simulation of critical synchronous dataflow graphs.
In Proceedings of the Design Automation Conference, pages
893-898, San Francisco, California, July 2006.
(PDF)
- [hua2006x1]
- S. Hua, G. Qu, and S. S.
Bhattacharyya.
Energy-efficient embedded software implementation on multiprocessor
system-on-chip with multiple voltages.
ACM Transactions on Embedded Computing Systems, 5(2):321-341, May
2006.
(PDF)
- [khan2006x1]
- M. Khandelia, N. K. Bambha, and
S. S. Bhattacharyya.
Contention-conscious transaction ordering in multiprocessor DSP systems.
IEEE Transactions on Signal Processing, 54(2):556-569, February
2006.
(PDF)
- [kian2006x2]
- V. Kianzad.
System Synthesis for Embedded Multiprocessors.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2006.
(PDF)
- [kian2006x1]
- V. Kianzad and S. S.
Bhattacharyya.
Efficient techniques for clustering and scheduling onto embedded
multiprocessors.
IEEE Transactions on Parallel and Distributed Systems,
17(7):667-680, July 2006.
(PDF)
- [ko2006x5]
- D. Ko.
System Synthesis for Image Processing Applications.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2006.
(PDF)
- [ko2006x4]
- M. Ko.
Integrated Software Synthesis for Signal Processing Applications.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2006.
(PDF)
- [ko2006x7]
- D. Ko and S. S. Bhattacharyya.
The pipeline decomposition tree: An analysis tool for multiprocessor
implementation of image processing applications.
In Proceedings of the International Conference on Hardware/Software
Codesign and System Synthesis, pages 52-57, Seoul, Korea, October
2006.
(PDF)
- [ko2006x2]
- D. Ko, C. Shen, S. S. Bhattacharyya,
and N. Goldsman.
Energy-driven partitioning of signal processing algorithms in sensor networks.
In Proceedings of the International Workshop on Embedded Computer
Systems: Architectures, Modeling, and Simulation, Lecture Notes in
Computer Science 4017, pages 142-154. Springer, Samos, Greece, July 2006.
(PDF)
- [ko2006x3]
- M. Ko, C. Shen, and S. S.
Bhattacharyya.
Memory-constrained block processing optimization for synthesis of DSP
software.
In Proceedings of the International Conference on Embedded Computer
Systems: Architectures, Modeling, and Simulation, pages 137-143,
Samos, Greece, July 2006.
(PDF)
- [ko2006x6]
- M. Ko, C. Zissulescu,
S. Puthenpurayil, S. S. Bhattacharyya, B. Kienhuis, and E. Deprettere.
Parameterized looped schedules for compact representation of execution
sequences.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 223-230, Steamboat
Springs, Colorado, September 2006.
(PDF)
- [murt2006x1]
- P. K. Murthy and S. S.
Bhattacharyya.
Memory Management for Synthesis of DSP Software.
CRC Press, 2006.
(PDF)
- [puth2006x1]
- S. Puthenpurayil, R. Gu, and S. S.
Bhattacharyya.
Compression techniques for minimum energy consumption.
In Proceedings of the Army Science Conference, Orlando, Florida,
November 2006.
(PDF)
- [saha2006x4]
- S. Saha, S. S. Bhattacharyya, and
W. Wolf.
A communication interface for multiprocessor signal processing systems.
In Proceedings of the IEEE Workshop on Embedded Systems for Real-Time
Multimedia, pages 127-132, Seoul, Korea, October 2006.
(PDF)
- [saha2006x2]
- S. Saha, S. Puthenpurayil, and
S. S. Bhattacharyya.
Dataflow transformations in high-level DSP system design.
In Proceedings of the International Symposium on System-on-Chip,
pages 131-136, Tampere, Finland, November 2006.
Invited paper.
(PDF)
- [saha2006x1]
- S. Saha, C. Shen, C. Hsu,
A. Veeraraghavan, A. Sussman, and S. S. Bhattacharyya.
Model-based OpenMP implementation of a 3D facial pose tracking system.
In Proceedings of the Workshop on Parallel and Distributed
Multimedia, pages 66-73, Columbus, Ohio, August 2006.
(PDF)
- [salm2006x1]
- P. Salmela, C. Shen, S. S.
Bhattacharyya, and J. Takala.
Register file partitioning with constraint programming.
In Proceedings of the International Symposium on System-on-Chip,
pages 137-140, Tampere, Finland, November 2006.
(PDF)
- [sen2006x2]
- M. Sen.
Model-based Hardware Design for Image Processing Systems.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2006.
(PDF)
- [sen2006x1]
- M. Sen, Y. Hemaraj, S. S.
Bhattacharyya, and R. Shekhar.
Reconfigurable image registration on FPGA platforms.
In Proceedings of the IEEE Biomedical Circuits and Systems
Conference, pages 154-157, London, UK, November 2006.
(PDF)
- [shen2006x1]
- C. Shen, C. Badr, K. Kordari,
S. S. Bhattacharyya, G. L. Blankenship, and N. Goldsman.
A rapid prototyping methodology for application-specific sensor networks.
In Proceedings of the IEEE International Workshop on Computer
Architecture for Machine Perception and Sensing, pages 130-135,
Montreal, Canada, September 2006.
(PDF)
- [teic2006x1]
- J. Teich and S. S. Bhattacharyya.
Analysis of dataflow programs with interval-limited data-rates.
Journal of VLSI Signal Processing Systems for Signal, Image, and Video
Technology, 43(2-3):247-258, June 2006.
(PDF)
- [bamb2005x1]
- N. Bambha and S. S. Bhattacharyya.
Joint application mapping/interconnect synthesis techniques for embedded
chip-scale multiprocessors.
IEEE Transactions on Parallel and Distributed Systems,
16(2):99-112, February 2005.
(PDF)
- [bamb2005x2]
- N. K. Bambha and S. S.
Bhattacharyya.
Communication strategies for shared bus embedded multiprocessors.
In Proceedings of the International Workshop on Embedded Software,
pages 21-24, Jersey City, New Jersey, September 2005.
(PDF)
- [hsu2005x3]
- C. Hsu and S. S. Bhattacharyya.
Integrating VSIPL support in the dataflow interchange format.
In Proceedings of the Annual Workshop on High Performance Embedded
Computing, pages 75-76, Lexington, Massachusetts, September 2005.
(PDF)
- [hsu2005x1]
- C. Hsu and S. S. Bhattacharyya.
Porting DSP applications across design tools using the dataflow interchange
format.
In Proceedings of the International Workshop on Rapid System
Prototyping, pages 40-46, Montreal, Canada, June 2005.
(PDF)
- [hsu2005x2]
- C. Hsu, M. Ko, and S. S.
Bhattacharyya.
Software synthesis from the dataflow interchange format.
In Proceedings of the International Workshop on Software and Compilers
for Embedded Systems, pages 37-49, Dallas, Texas, September 2005.
(PDF)
- [kian2005x2]
- V. Kianzad, S. Saha,
J. Schlessman, G. Aggarwal, S. S. Bhattacharyya, W. Wolf, and R. Chellappa.
An architectural level design methodology for embedded face detection.
In Proceedings of the International Conference on Hardware/Software
Codesign and System Synthesis, pages 136-141, Jersey City, New
Jersey, September 2005.
(PDF)
- [ko2005x2]
- D. Ko and S. S. Bhattacharyya.
Dynamic configuration of dataflow graph topology for DSP system design.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages V-69-V-72, Philadelphia, Pennsylvania,
March 2005.
(PDF)
- [ko2005x5]
- D. Ko and S. S. Bhattacharyya.
Modeling and optimization of buffering trade-offs for hardware implementation
of image processing applications.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 591-596, Athens, Greece, November 2005.
(PDF)
- [ko2005x3]
- D. Ko and S. S. Bhattacharyya.
Modeling of block-based DSP systems.
Journal of VLSI Signal Processing Systems for Signal, Image, and Video
Technology, 40(3):289-299, July 2005.
(PDF)
- [sen2005x1]
- M. Sen, S. S. Bhattacharyya, T. Lv,
and W. Wolf.
Modeling image processing systems with homogeneous parameterized dataflow
graphs.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages V-133-V-136, Philadelphia, Pennsylvania,
March 2005.
(PDF)
- [sen2005x2]
- M. Sen, I. Corretjer, F. Haim,
S. Saha, J. Schlessman, S. S. Bhattacharyya, and W. Wolf.
Computer vision on FPGAs: Design methodology and its application to gesture
recognition.
In Proceedings of the IEEE Workshop on Embedded Computer Vision,
pages CD-ROM version, 8 pages, San Diego, California, June 2005.
(PDF)
- [bamb2004x4]
- N. K. Bambha.
Communication-driven Codesign for Multiprocessor Systems.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, 2004.
(PDF)
- [bamb2004x3]
- N. K. Bambha and S. S.
Bhattacharyya.
Interconnect synthesis for systems on chip.
In Proceedings of the IEEE International Workshop on System on Chip for
Real Time Processing, pages 263-268, Banff, Canada, July 2004.
(PDF)
- [bamb2004x1]
- N. K. Bambha, S. S. Bhattacharyya,
J. Teich, and E. Zitzler.
Systematic integration of parameterized local search in evolutionary
algorithms.
IEEE Transactions on Evolutionary Computation, 8(2):137-155,
April 2004.
(PDF)
- [bhat2004x1]
- S. S. Bhattacharyya and P. K.
Murthy.
The CBP parameter --- a module characterization approach for DSP software
optimization.
Journal of VLSI Signal Processing Systems for Signal, Image, and Video
Technology, 38(2):131-146, September 2004.
(PDF)
- [chan2004x1]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K. J. R. Liu.
The hierarchical timing pair model for multirate DSP applications.
IEEE Transactions on Signal Processing, 52(5):1209-1217, May
2004.
(PDF)
- [hsu2004x2]
- C. Hsu and S. S. Bhattacharyya.
Dataflow interchange format version 0.2.
Technical Report UMIACS-TR-2004-66, Institute for Advanced Computer Studies,
University of Maryland at College Park, November 2004.
Also Computer Science Technical Report CS-TR-4624.
(PDF)
- [hsu2004x1]
- C. Hsu, F. Keceli, M. Ko,
S. Shahparnia, and S. S. Bhattacharyya.
DIF: An interchange format for dataflow-based design tools.
In Proceedings of the International Workshop on Systems, Architectures,
Modeling, and Simulation, pages 423-432, Samos, Greece, July 2004.
(PDF)
- [kian2004x1]
- V. Kianzad and S. S.
Bhattacharyya.
CHARMED: A multiobjective cosynthesis framework for multi-mode embedded
systems.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 28-40, Galveston,
Texas, September 2004.
(PDF)
- [ko2004x2]
- M. Ko, P. K. Murthy, and S. S.
Bhattacharyya.
Compact procedural implementation in DSP software synthesis through recursive
graph decomposition.
In Proceedings of the International Workshop on Software and Compilers
for Embedded Systems, pages 47-61, Amsterdam, The Netherlands,
September 2004.
(PDF)
- [ko2004x3]
- M. Ko, P. K. Murthy, and S. S.
Bhattacharyya.
Compact procedural synthesis of DSP software through recursive graph
decomposition.
Technical Report UMIACS-TR-2004-41, Institute for Advanced Computer Studies,
University of Maryland at College Park, June 2004.
Also Computer Science Technical Report CS-TR-4599.
(PDF)
- [murt2004x1]
- P. K. Murthy and S. S.
Bhattacharyya.
Buffer merging --- a powerful technique for reducing memory requirements of
synchronous dataflow specifications.
ACM Transactions on Design Automation of Electronic Systems,
9(2):212-237, April 2004.
(PDF)
- [sen2004x1]
- M. Sen and S. S. Bhattacharyya.
Systematic exploitation of data parallelism in hardware synthesis of DSP
applications.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages V-229-V-232, Montreal, Canada, May 2004.
(PDF)
- [teic2004x1]
- J. Teich and S. S. Bhattacharyya.
Analysis of dataflow programs with interval-limited data-rates.
In Proceedings of the International Workshop on Systems, Architectures,
Modeling, and Simulation, pages 507-518, Samos, Greece, July 2004.
(PDF)
- [varm2004x1]
- A. Varma and S. S. Bhattacharyya.
Java-through-C compilation: An enabling technology for Java in embedded
systems.
In Proceedings of the Design Automation and Test in Europe Conference and
Exhibition, Designer's Forum, pages 161-167, Paris, France, February
2004.
(PDF)
- [bamb2003x1]
- N. K. Bambha, S. S. Bhattacharyya,
and G. Euliss.
Design considerations for optically connected systems on chip.
In Proceedings of the IEEE International Workshop on System on Chip for
Real Time Processing, pages 299-303, Calgary, Canada, June 2003.
(PDF)
- [bhat2003x1]
- S. S. Bhattacharyya,
E. Deprettere, and J. Teich, editors.
Domain-Specific Processors: Systems, Architectures, Modeling, and
Simulation.
Marcel Dekker, Inc., 2003.
(PDF)
- [hua2003x3]
- S. Hua, G. Qu, and S. S.
Bhattacharyya.
Energy-efficient multi-processor implementation of embedded software.
In Proceedings of the International Workshop on Embedded Software,
pages 257-273, Philadelphia, Pennsylvania, October 2003.
(PDF)
- [hua2003x1]
- S. Hua, G. Qu, and S. S.
Bhattacharyya.
Energy reduction techniques for multimedia applications with tolerance to
deadline misses.
In Proceedings of the Design Automation Conference, pages
131-136, Anaheim, California, June 2003.
(PDF)
- [hua2003x2]
- S. Hua, G. Qu, and S. S.
Bhattacharyya.
Exploring the probabilistic design space of multimedia systems.
In Proceedings of the International Workshop on Rapid System
Prototyping, pages 233-240, San Diego, California, June 2003.
(PDF)
- [kian2003x1]
- V. Kianzad and S. S.
Bhattacharyya.
A comparison of clustering and scheduling techniques for embedded
multiprocessor systems.
Technical Report UMIACS-TR-2003-114, Institute for Advanced Computer Studies,
University of Maryland at College Park, December 2003.
Also Computer Science Technical Report CS-TR-4546.
(PDF)
- [ko2003x1]
- D. Ko and S. S. Bhattacharyya.
Modeling of block-based DSP systems.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 381-386, Seoul, Korea, August 2003.
(PDF)
- [ko2003x2]
- M. Ko and S. S. Bhattacharyya.
Data partitioning for DSP software synthesis.
In Proceedings of the International Workshop on Software and Compilers
for Embedded Systems, pages 344-358, Vienna, Austria, September 2003.
(PDF)
- [loha2003x1]
- S. Lohani and S. S. Bhattacharyya.
Goal-driven reconfiguration of polymorphous architectures.
In S. S. Bhattacharyya, E. Depretter, and J. Teich, editors,
Domain-Specific Processors: Systems, Architectures, Modeling and
Simulation, pages 151-170. Marcel Dekker, Inc., 2003.
- [rine2003x1]
- M. Rinehart, V. Kianzad, and S. S.
Bhattacharyya.
A modular genetic algorithm for scheduling task graphs.
Technical Report UMIACS-TR-2003-66, Institute for Advanced Computer Studies,
University of Maryland at College Park, June 2003.
Also Computer Science Technical Report CS-TR-4497.
(PDF)
- [spiv2003x2]
- G. Spivey, S. S. Bhattacharyya,
and K. Nakajima.
Logic foundry: Rapid prototyping for FPGA-based DSP systems.
EURASIP Journal on Applied Signal Processing, 2003(6):565-579,
May 2003.
(PDF)
- [spiv2003x1]
- G. Spivey, S. S. Bhattacharyya,
and K. Nakajima.
Logic foundry: Rapid prototyping of FPGA-based DSP systems.
In Proceedings of the Asia and South Pacific Design Automation
Conference, pages 374-381, Kitakyushu, Japan, January 2003.
(PDF)
- [bamb2002x3]
- N. Bambha and S. S. Bhattacharyya.
System synthesis for optically-connected, multiprocessors on-chip.
In W. Badawy and G. A. Julien, editors, System on Chip for Real-time
Systems, pages 339-448. Kluwer Academic Publishers, 2002.
(PDF)
- [bamb2002x4]
- N. Bambha and S. S. Bhattacharyya.
Techniques for co-design of optically-connected embedded multiprocessors.
In Proceedings of the Annual Workshop on High Performance Embedded
Computing, pages 97-99, Lexington, Massachusetts, September 2002.
(PDF)
- [bamb2002x1]
- N. Bambha, V. Kianzad,
M. Khandelia, and S. S. Bhattacharyya.
Intermediate representations for design automation of multiprocessor DSP
systems.
Journal of Design Automation for Embedded Systems, 7(4):307-323,
November 2002.
(PDF)
- [bhat2002x2]
- B. Bhattacharya and S. S.
Bhattacharyya.
Consistency analysis of reconfigurable dataflow specifications.
In E. F. Deprettere, J. Teich, and S. Vassiliadis, editors, Embedded
Processor Design Challenges, Lecture Notes in Computer Science, pages
1-17. Springer, 2002.
(PDF)
- [bhat2002x1]
- S. S. Bhattacharyya.
Hardware/software co-synthesis of DSP systems.
In Y. H. Hu, editor, Programmable Digital Signal Processors:
Architecture, Programming, and Applications, pages 333-378. Marcel
Dekker, Inc., 2002.
(PDF)
- [bhat2002x3]
- S. S. Bhattacharyya, E. Cheong,
J. Davis II, M. Goel, C. Hylands, B. Kienhuis, E. A. Lee, J. Liu, X. Liu,
L. Muliadi, S. Neuendorffer, J. Reekie, N. Smyth, J. Tsay, B. Vogel,
W. Williams, Y. Xiong, and H. Zheng.
Heterogeneous concurrent modeling and design in java.
Technical Report UCB/ERL M02/23, Department of Electrical Engineering and
Computer Sciences, University of California at Berkeley, August 2002.
(PDF)
- [chan2002x2]
- N. Chandrachoodan.
Performance Analysis and Hierarchical Timing for DSP System
Synthesis.
PhD thesis, Department of Electrical and Computer Engineering, University of
Maryland, College Park, August 2002.
(PDF)
- [chan2002x1]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K. J. Ray Liu.
High-level synthesis of DSP applications using adaptive negative cycle
detection.
EURASIP Journal on Applied Signal Processing, 2002(9):893-907,
September 2002.
(PDF)
- [kece2002x1]
- F. Keceli, M. Ko, S. Shahparnia,
and S. S. Bhattacharyya.
First version of a dataflow interchange format.
Technical Report UMIACS-TR-2002-98, Institute for Advanced Computer Studies,
University of Maryland at College Park, November 2002.
Also Computer Science Technical Report CS-TR-4418.
(PDF)
- [loha2002x2]
- S. Lohani and S. S. Bhattacharyya.
Goal-driven reconfiguration of polymorphous architectures.
In Proceedings of the International Workshop on Systems, Architectures,
Modeling, and Simulation, Samos, Greece, July 2002.
(PDF)
- [loha2002x1]
- S. Lohani and S. S. Bhattacharyya.
System synthesis for polymorphous computing architectures.
Technical Report UMIACS-TR-2002-12, Institute for Advanced Computer Studies,
University of Maryland at College Park, February 2002.
Also Computer Science Technical Report CS-TR-4330.
(PostScript)
(PDF)
- [spiv2002x3]
- G. Spivey, S. S. Bhattacharyya,
and K. Nakajima.
A component architecture for FPGA-based, DSP system design.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 41-51, San Jose,
California, July 2002.
(PDF)
- [spiv2002x1]
- G. Spivey, S. S. Bhattacharyya,
and Kazuo Nakajima.
Logic foundry: A rapid prototyping tool for FPGA-based DSP systems.
Technical Report UMIACS-TR-2002-29, Institute for Advanced Computer Studies,
University of Maryland at College Park, March 2002.
Also Computer Science Technical Report CS-TR-4349.
(PDF)
- [bamb2001x1]
- N. Bambha, S. S. Bhattacharyya,
J. Teich, and E. Zitzler.
Hybrid search strategies for dynamic voltage scaling in embedded
multiprocessors.
In Proceedings of the International Workshop on Hardware/Software
Codesign, pages 243-248, Copenhagen, Denmark, April 2001.
(PDF)
- [bhat2001x2]
- B. Bhattacharya and S. S.
Bhattacharyya.
Parameterized dataflow modeling for DSP systems.
IEEE Transactions on Signal Processing, 49(10):2408-2421, October
2001.
(PDF)
- [bhat2001x3]
- S. S. Bhattacharyya, N. Bambha,
M. Khandelia, and V. Kianzad.
Mapping DSP applications onto self-timed multiprocessors.
In Proceedings of the IEEE Asilomar Conference on Signals, Systems, and
Computers, volume 1, pages 441-448, Pacific Grove, California,
November 2001.
Invited paper.
(PDF)
- [chan2001x2]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K. J. R. Liu.
Adaptive negative cycle detection in dynamic graphs.
In Proceedings of the International Symposium on Circuits and
Systems, pages V-163-V-166, Sydney, Australia, May 2001.
(PDF)
- [chan2001x3]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K. J. R. Liu.
An efficient timing model for hardware implementation of multirate dataflow
graphs.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, volume 2, pages 1153-1156, Salt Lake City, Utah,
May 2001.
(PDF)
- [chan2001x1]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K. J. R. Liu.
The hierarchical timing pair model.
In Proceedings of the International Symposium on Circuits and
Systems, pages V-367-V-370, Sydney, Australia, May 2001.
(PDF)
- [kian2001x2]
- V. Kianzad and S. S.
Bhattacharyya.
Multiprocessor clustering for embedded system implementation.
Technical Report UMIACS-TR-2001-52, Institute for Advanced Computer Studies,
University of Maryland at College Park, June 2001.
Also Computer Science Technical Report CS-TR-4272.
(PDF)
- [kian2001x1]
- V. Kianzad and S. S.
Bhattacharyya.
Multiprocessor clustering for embedded systems.
In Proceedings of the European Conference on Parallel Computing,
pages 697-701, Manchester, United Kingdom, August 2001.
(PDF)
- [murt2001x1]
- P. K. Murthy and S. S.
Bhattacharyya.
Shared buffer implementations of signal processing systems using lifetime
analysis techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(2):177-198, February 2001.
(PDF)
- [bamb2000x1]
- N. K. Bambha and S. S.
Bhattacharyya.
A joint power/performance optimization technique for multiprocessor systems
using a period graph construct.
In Proceedings of the International Symposium on System Synthesis,
pages 91-97, Madrid, Spain, September 2000.
(PDF)
- [bamb2000x2]
- N. K. Bambha and S. S.
Bhattacharyya.
A period graph throughput estimator for multiprocessor systems.
Technical Report UMIACS-TR-2000-49, Institute for Advanced Computer Studies,
University of Maryland at College Park, July 2000.
Also Computer Science Technical Report CS-TR-4159.
(PDF)
- [bhat2000x4]
- B. Bhattacharya and S. S.
Bhattacharyya.
Parameterized dataflow modeling of DSP systems.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages 1948-1951, Istanbul, Turkey, June 2000.
(PDF)
- [bhat2000x1]
- B. Bhattacharya and S. S.
Bhattacharyya.
Quasi-static scheduling of reconfigurable dataflow graphs for DSP systems.
In Proceedings of the International Workshop on Rapid System
Prototyping, pages 84-89, Paris, France, June 2000.
(PDF)
- [bhat2000x3]
- S. S. Bhattacharyya and P. K.
Murthy.
The CBP parameter --- a useful annotation to aid block diagram compilers for
DSP.
In Proceedings of the International Symposium on Circuits and
Systems, pages IV-209-IV-212, Geneva, Switzerland, May 2000.
(PDF)
- [bhat2000x6]
- S. S. Bhattacharyya, R. Leupers,
and P. Marwedel.
Software synthesis and code generation for DSP.
IEEE Transactions on Circuits and Systems --- II: Analog and Digital
Signal Processing, 47(9):849-875, September 2000.
(PDF)
- [bhat2000x5]
- S. S. Bhattacharyya, S. Sriram,
and E. A. Lee.
Resynchronization for multiprocessor DSP systems.
IEEE Transactions on Circuits and Systems --- I: Fundamental Theory and
Applications, 47(11):1597-1609, November 2000.
(PDF)
- [chan2000x1]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K. J. R. Liu.
The hierarchical timing pair model for synchronous dataflow systems.
Technical Report UMIACS-TR-2000-75, Institute for Advanced Computer Studies,
University of Maryland at College Park, November 2000.
Also Computer Science Technical Report CS-TR-4198.
(PDF)
- [jaco2000x1]
- B. L. Jacob and S. S.
Bhattacharyya.
Real-time memory management: Compile-time techniques and run-time mechanisms
that enable the use of caches in real-time systems.
Technical Report UMIACS-TR-2000-60, Institute for Advanced Computer Studies,
University of Maryland at College Park, September 2000.
Also Computer Science Technical Report CS-TR-4178.
(PDF)
- [khan2000x1]
- M. Khandelia and S. S.
Bhattacharyya.
Contention-conscious transaction ordering in embedded multiprocessor systems.
Technical Report UMIACS-TR-2000-09, Institute for Advanced Computer Studies,
University of Maryland at College Park, March 2000.
Also Computer Science Technical Report CS-TR-4109.
(PostScript)
(PDF)
- [khan2000x2]
- M. Khandelia and S. S.
Bhattacharyya.
Contention-conscious transaction ordering in embedded multiprocessors.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 276-285, Boston,
Massachusetts, July 2000.
(PDF)
- [murt2000x2]
- P. K. Murthy and S. S.
Bhattacharyya.
Buffer merging --- a powerful technique for reducing memory requirements of
synchronous dataflow specifications.
Technical Report UMIACS-TR-2000-20, Institute for Advanced Computer Studies,
University of Maryland at College Park, April 2000.
Also Computer Science Technical Report CS-TR-4126.
(PostScript)
(PDF)
- [murt2000x1]
- P. K. Murthy and S. S.
Bhattacharyya.
Shared memory implementations of synchronous dataflow specifications.
In Proceedings of the Design, Automation and Test in Europe Conference
and Exhibition, pages 404-410, March 2000.
Paris, France.
(PDF)
- [murt2000x3]
- P. K. Murthy and S. S.
Bhattacharyya.
Systematic consolidation of input and output buffers in synchronous dataflow
specifications.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 673-682, Lafayette, Louisiana, October 2000.
(PDF)
- [srir2000x1]
- S. Sriram and S. S. Bhattacharyya.
Embedded Multiprocessors: Scheduling and Synchronization.
Marcel Dekker, Inc., 2000.
(PDF)
- [zitz2000x3]
- E. Zitzler, J. Teich, and S. S.
Bhattacharyya.
Evolutionary algorithms for the synthesis of embedded software.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(4):452-456, August 2000.
(PDF)
- [zitz2000x1]
- E. Zitzler, J. Teich, and S. S.
Bhattacharyya.
Multidimensional exploration of software implementations for DSP algorithms.
Journal of VLSI Signal Processing Systems for Signal, Image, and Video
Technology, 24(1):83-98, February 2000.
(PDF)
- [zitz2000x2]
- E. Zitzler, J. Teich, and S. S.
Bhattacharyya.
Optimizing the efficiency of parameterized local search within global search: A
preliminary study.
In Proceedings of the Congress on Evolutionary Computation, pages
365-372, San Diego, California, July 2000.
(PDF)
- [bhat1999x9]
- B. Bhattacharya and S. S.
Bhattacharyya.
Parameterized modeling and scheduling of dataflow graphs.
Technical Report UMIACS-TR-99-73, Institute for Advanced Computer Studies,
University of Maryland at College Park, December 1999.
Also Computer Science Technical Report CS-TR-4083.
(PostScript)
(PDF)
- [bhat1999x3]
- S. S. Bhattacharyya.
Optimization trade-offs in the synthesis of software for embedded DSP.
In Proceedings of the International Workshop on Compiler and Architecture
Support for Embedded Systems, pages 97-102, October 1999.
Washington, D. C.
(PostScript)
(PDF)
- [bhat1999x7]
- S. S. Bhattacharyya and P. K.
Murthy.
The CBP parameter --- a useful annotation to aid SDF compilers.
Technical Report UMIACS-TR-99-56, Institute for Advanced Computer Studies,
University of Maryland at College Park, September 1999.
Also Computer Science Technical Report CS-TR-4062.
(PostScript)
(PDF)
- [bhat1999x8]
- S. S. Bhattacharyya, R. Leupers,
and P. Marwedel.
Software synthesis and code generation for signal processing systems.
Technical Report UMIACS-TR-99-57, Institute for Advanced Computer Studies,
University of Maryland at College Park, September 1999.
Also Computer Science Technical Report CS-TR-4063.
(PostScript)
- [bhat1999x1]
- S. S. Bhattacharyya, P. K. Murthy,
and E. A. Lee.
Synthesis of embedded software from synchronous dataflow specifications.
Journal of VLSI Signal Processing Systems for Signal, Image, and Video
Technology, 21(2):151-166, June 1999.
(PDF)
- [chan1999x1]
- N. Chandrachoodan, S. S.
Bhattacharyya, and K.J. R. Liu.
Negative cycle detection in dynamic graphs.
Technical Report UMIACS-TR-99-59, Institute for Advanced Computer Studies,
University of Maryland at College Park, September 1999.
Also Computer Science Technical Report CS-TR-4065.
(PostScript)
- [murt1999x4]
- P. K. Murthy and S. S.
Bhattacharyya.
Approximation algorithms and heuristics for the dynamic storage allocation
problem.
Technical Report UMIACS-TR-99-31, Institute for Advanced Computer Studies,
University of Maryland at College Park, June 1999.
Also Computer Science Technical Report CS-TR-4024.
(PDF)
- [murt1999x3]
- P. K. Murthy and S. S.
Bhattacharyya.
A buffer merging technique for reducing memory requirements of synchronous
dataflow specifications.
In Proceedings of the International Symposium on System Synthesis,
pages 78-84, San Jose, California, November 1999.
(PDF)
- [murt1999x1]
- P. K. Murthy and S. S.
Bhattacharyya.
Shared memory implementations of synchronous dataflow specifications using
lifetime analysis techniques.
Technical Report UMIACS-TR-99-32, Institute for Advanced Computer Studies,
University of Maryland at College Park, June 1999.
(PostScript)
- [teic1999x2]
- J. Teich, E. Zitzler, and S. S.
Bhattacharyya.
3D exploration of software schedules for DSP algorithms.
In Proceedings of the International Workshop on Hardware/Software
Codesign, pages 168-172, May 1999.
Rome, Italy.
(PDF)
- [zitz1999x1]
- E. Zitzler, J. Teich, and S. S.
Bhattacharyya.
Evolutionary algorithm based exploration of software schedules for digital
signal processors.
In Proceedings of the Genetic and Evolutionary Computation
Conference, pages 1762-1769, Orlando, Florida, July 1999.
(PDF)
- [zitz1999x4]
- E. Zitzler, J. Teich, and S. S.
Bhattacharyya.
Optimized software synthesis for DSP using randomization techniques.
Technical report, Computer Engineering and Communication Networks Laboratory,
Swiss Federal Institute of Technology, Zurich, July 1999.
Revised version of teic1998x1.
(PostScript)
- [bhat1998x2]
- S. S. Bhattacharyya, S. Sriram,
and E. A. Lee.
Resynchronization for multiprocessor DSP implementation --- part 1:
Maximum-throughput resynchronization.
Technical report, Digital Signal Processing Laboratory, University of Maryland,
College Park, July 1998.
(PostScript)
- [bhat1998x3]
- S. S. Bhattacharyya, S. Sriram,
and E. A. Lee.
Resynchronization for multiprocessor DSP implementation --- part 2:
Latency-constrained resynchronization.
Technical report, Digital Signal Processing Laboratory, University of Maryland,
College Park, July 1998.
(PostScript)
- [teic1998x3]
- J. Teich, E. Zitzler, and S. S.
Bhattacharyya.
Buffer memory optimization in DSP applications --- an evolutionary approach.
In Proceedings of the International Conference on Parallel Problem
Solving from Nature, pages 885-894, Amsterdam, The Netherlands,
September 1998.
(PostScript)
(PDF)
- [teic1998x1]
- J. Teich, E. Zitzler, and S. S.
Bhattacharyya.
Optimized software synthesis for digital signal processing algorithms --- an
evolutionary approach.
Technical report, Computer Engineering and Communication Networks Laboratory,
Swiss Federal Institute of Technology, Zurich, January 1998.
(PostScript)
- [teic1998x2]
- J. Teich, E. Zitzler, and S. S.
Bhattacharyya.
Optimized software synthesis for digital signal processing algorithms --- an
evolutionary approach.
In Proceedings of the IEEE Workshop on Signal Processing Systems,
pages 589-598, October 1998.
Boston, Massachusetts.
(PostScript)
(PDF)
- [bhat1997x2]
- S. S. Bhattacharyya, P. K. Murthy,
and E. A. Lee.
APGAN and RPMC: Complementary heuristics for translating DSP block diagrams
into efficient software implementations.
Journal of Design Automation for Embedded Systems, 2(1):33-60,
January 1997.
(PDF)
- [bhat1997x1]
- S. S. Bhattacharyya, S. Sriram,
and E. A. Lee.
Optimizing synchronization in multiprocessor DSP systems.
IEEE Transactions on Signal Processing, 45(6):1605-1618, June
1997.
(PDF)
- [murt1997x1]
- P. K. Murthy, S. S. Bhattacharyya,
and E. A. Lee.
Joint minimization of code and data for synchronous dataflow programs.
Journal of Formal Methods in System Design, 11(1):41-70, July
1997.
(PDF)
- [bhat1996x5]
- S. S. Bhattacharyya, P. K. Murthy,
and E. A. Lee.
Software Synthesis from Dataflow Graphs.
Kluwer Academic Publishers, 1996.
(PDF)
- [bhat1996x2]
- S. S. Bhattacharyya, S. Sriram,
and E. A. Lee.
Latency-constrained resynchronization for multiprocessor DSP implementation.
In Proceedings of the International Conference on Application Specific
Systems, Architectures, and Processors, pages 365-380, August 1996.
Chicago, Illinois.
(PostScript)
- [bhat1996x1]
- S. S. Bhattacharyya, S. Sriram,
and E. A. Lee.
Self-timed resynchronization: A post-optimization for static multiprocessor
schedules.
In Proceedings of the International Parallel Processing Symposium,
pages 199-205, April 1996.
Honolulu, Hawaii.
(PostScript)
- [bhat1995x3]
- S. S. Bhattacharyya, J. T. Buck,
S. Ha, and E. A. Lee.
Generating compact code from dataflow specifications of multirate signal
processing algorithms.
IEEE Transactions on Circuits and Systems --- I: Fundamental Theory and
Applications, 42(3):138-150, March 1995.
(PDF)
- [bhat1995x7]
- S. S. Bhattacharyya, P. K. Murthy,
and E. A. Lee.
Converting graphical DSP programs into memory-constrained software
prototypes.
In Proceedings of the International Workshop on Rapid System
Prototyping, pages 194-200, Chapel Hill, North Carolina, June 1995.
(PDF)
- [bhat1995x1]
- S. S. Bhattacharyya, P. K. Murthy,
and E. A. Lee.
Optimal parenthesization of lexical orderings for DSP block diagrams.
In Proceedings of the International Workshop on VLSI Signal
Processing, pages 177-186. IEEE press, October 1995.
Sakai, Osaka, Japan.
(PDF)
- [bhat1995x8]
- S. S. Bhattacharyya, P. K. Murthy,
and E. A. Lee.
Renesting single appearance schedules to minimize buffer memory.
Technical report, Electronics Research Laboratory, University of California at
Berkeley, April 1995.
(PDF)
- [pino1995x3]
- J. L. Pino, S. S. Bhattacharyya,
and E. A. Lee.
A hierarchical multiprocessor scheduling framework for synchronous dataflow
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Technical report, Electronics Research Laboratory, University of California at
Berkeley, May 1995.
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A hierarchical multiprocessor scheduling system for DSP applications.
In Proceedings of the IEEE Asilomar Conference on Signals, Systems, and
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Compiling Dataflow Programs for Digital Signal Processing.
PhD thesis, Department of Electrical Engineering and Computer Sciences,
University of California at Berkeley, July 1994.
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Looped schedules for dataflow descriptions of multirate signal processing
algorithms.
Journal of Formal Methods in System Design, pages 183-205,
December 1994.
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Memory management for dataflow programming of multirate signal processing
algorithms.
IEEE Transactions on Signal Processing, 42(5):1190-1201, May
1994.
(PDF)
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and E. A. Lee.
Combined code and data minimization for synchronous dataflow programs.
Technical Report M94/93, Department of Electrical Engineering and Computer
Sciences, University of California at Berkeley, November 1994.
(PostScript)
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and E. A. Lee.
Minimizing memory requirements for chain-structured synchronous dataflow
programs.
In Proceedings of the International Conference on Acoustics, Speech, and
Signal Processing, pages 453-456 vol.2, Adelaide, SA, Australia,
April 1994.
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Scheduling synchronous dataflow graphs for efficient looping.
Journal of VLSI Signal Processing, 6(3):271-288, December 1993.
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Memory management for synchronous dataflow programs.
Technical Report UCB/ERL M92/128, Electronics Research Laboratory, University
of California at Berkeley, 1992.
(PDF)